iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing

Abstract

In recent years, $$\hbox {optical character recognition (OCR)}$$ optical character recognition (OCR) systems have been used to digitally preserve historical archives. To transcribe historical archives into a machine-readable form, first, the documents are scanned, then an $$\hbox {OCR}$$ OCR is applied. In order to digitize documents without the need to remove them from where they are archived, it is valuable to have a portable device that combines scanning and $$\hbox {OCR}$$ OCR capabilities. Nowadays, there exist many commercial and open-source document digitization techniques, which are optimized for contemporary documents. However, they fail to give sufficient text recognition accuracy for transcribing historical documents due to the severe quality degradation of such documents. On the contrary, the anyOCR system, which is designed to mainly digitize historical documents, provides high accuracy. However, this comes at a cost of high computational complexity resulting in long runtime and high power consumption. To tackle these challenges, we propose a low power energy-efficient accelerator with real-time capabilities called iDocChip, which is a configurable hybrid hardware-software programmable $$\hbox {System-on-Chip (SoC)}$$ System-on-Chip (SoC) based on anyOCR for digitizing historical documents. In this paper, we focus on one of the most crucial processing steps in the anyOCR system: Text and Image Segmentation, which makes use of a multi-resolution morphology-based algorithm. Moreover, an optimized $$\hbox {FPGA}$$ FPGA -based hybrid architecture of this anyOCR step along with its optimized software implementations are presented. We demonstrate our results on multiple embedded and general-purpose platforms with respect to runtime and power consumption. The resulting hardware accelerator outperforms the existing anyOCR by 6.2$$\times$$ × , while achieving 207$$\times$$ × higher energy-efficiency and maintaining its high accuracy.

iDocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

“…4. Resource utilization of the hardware implementation for the end-to-end OCR iDocChip system (this work) compared to the total resource utilization of the previous separately implemented pipeline steps [26][27][28][29] The original anyOCR is a Python-based software that uses the multi-dimensional image processing library [84] and runs on a multi-threaded Intel ® Core™ i7-4790T with Turbo Boost up to 3.9 GHz for one active core and 2.7 GHz for four active cores. For further analysis, the runtime and energy efficiency of the optimized software implementations are examined on different platforms; see Table 5.…”

“…However, the software part of this hybrid accelerator is very inefficient due to the sequential and time-consuming union-find algorithm. Hence, in [27], we have presented a new optimized heterogeneous architecture based on an improved text and image segmentation algorithm. The resulting accelerator has reduced the runtime and improved the energy efficiency of the previous accelerator stated in [30] by 40% and 46%, respectively.…”

“…Moreover, none of the previous publications targeted embedded platforms or focused on designing low-power real-time systems. Although in our previous publications [ 26 , 27 , 28 , 29 , 30 ], we have presented hardware architectures for each of the four OCR pipelines (see Section 4 ), these implementations are optimized for their corresponding step, and they require changes to integrate them into a single system.…”

“…While the character recognition step of anyOCR is universal and suitable for both contemporary and historical documents, the binarization and layout analysis steps are designed with a special emphasis on histori-cal documents, as the historical documents are typically more physically deteriorated than contemporary documents and have complex layout structure. In previous publications [26][27][28][29][30], we have presented hardware architectures for each of these four pipeline steps. However, these architectures are separately developed and require modifications to put all pipelines together.…”

“…In previous publications [ 26 , 27 , 28 , 29 , 30 ], we have presented hardware architectures for each of these four pipeline steps. However, these architectures are separately developed and require modifications to put all pipelines together.…”