Proceedings of the 12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005.
DOI: 10.1109/ipfa.2005.1469124
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Identification of some key parameters for photoelectric laser simulation of IC: an experimental approach

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Cited by 4 publications
(3 citation statements)
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References 17 publications
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“…Future work characterizing PLS effect on a PMOS transistor under PLS should be led. The test with a pulsed laser will also be conducted to explore higher laser energy ranges [14]. …”
Section: Discussionmentioning
confidence: 99%
“…Future work characterizing PLS effect on a PMOS transistor under PLS should be led. The test with a pulsed laser will also be conducted to explore higher laser energy ranges [14]. …”
Section: Discussionmentioning
confidence: 99%
“…Future work will characterize PLS effect on simple logic gates or MOS inverter under PLS. The test with a pulsed laser will also be conducted to explore higher laser energy ranges [17].…”
Section: Discussionmentioning
confidence: 99%
“…Some applications are local electrical testing inside integrated circuits by laser. The carrier injection process namely photoelectric laser stimulation (PLS) can be synchronized with static or dynamic electrical signals in failure-analysis tests [129], or after the fabrication as a parametric measurement, improving the investigation time because of the high repetition rate capability and the simplicity of laser experiments compared to electrical methods. The laser approach is also attractive to emulate more generally accelerated aging or radiative effects to test their robustness in hard condition environments (e.g.…”
Section: Applications In Microelectronicsmentioning
confidence: 99%