Identification of Random/Clustered TSV Defects in 3D IC During Pre-Bond Testing

Maity, Dilip Kumar; Roy, Surajit Kumar; Giri, Chandan

doi:10.1007/s10836-019-05824-w

Cited by 5 publications

(1 citation statement)

References 31 publications

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“…During the IC fabrication, there may be a chance for TSV to become defective and it must be identified to increase the performance of the system. To resolve this problem, many faulty TSV detection techniques are introduced [15], [16], [17], [18], [19].…”

Section: Introductionmentioning

confidence: 99%

A Genetic Algorithm-Based Metaheuristic Approach for Test Cost Optimization of 3D SIC

Kaibartta¹,

Biswas²,

Pal³

et al. 2021

IEEE Access

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Demand for small, multi functional, high performance electronic product with less power consumption is increasing rapidly. To meet the demand, IC design has been shifted from two dimensional integrated circuit (2D-IC) to three dimensional integrated circuit (3D-IC), where multiple device layers are stacked together to create stacked integrated circuit (SIC). This results the complexity in 3D SIC architecture and increase in the number of fault-sites. Therefore, testing of SIC has become complicated. Consequently, the test data volume also grows in proportion to the number of cores in the SIC, since each core is associated with one or more tests, which leads to longer test times. Test cost of IC which depends on test time, associated hardware to test the cores and the power dissipated at the time of test, can be represented as a weighted sum of test time and the associated hardware to test the core with power considered as the test constraint. As a result an efficient test plan is required to co-optimize test time and hardware under certain power constraint. The objective of our work is to design an efficient test plan both for non stacked IC ( i.e. SIC with single chip) and 3D stacked IC (i.e. SIC with multiple chips) under a power constraint, where each chip is provided with IEEE 1149.1 architecture. An existing cost model is used for calculating the test cost. Initially we propose First fit based two dimensional (2D) Bin Packing optimization algorithm for minimizing the test cost of non stacked IC. However, the method produces sub-optimal result in comparison to earlier reported work. Knowing the complexity of 3D SIC, Genetic algorithm based metaheuristic approach is next proposed in this paper. It is applied on several ITC02 benchmark circuits and the experimental result shows the efficacy of the proposed algorithm in comparison to earlier works.

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