Idempotent processor architecture

Abstract

Improving architectural energy efficiency is important to address diminishing energy efficiency gains from technology scaling. At the same time, limiting hardware complexity is also important. This paper presents a new processor architecture, the idempotent processor architecture, that advances both of these directions by presenting a new execution paradigm that allows speculative execution without the need for hardware checkpoints to recover from misspeculation, instead using only re-execution to recover. Idempotent processors execute programs as a sequence of compilerconstructed idempotent (re-executable) regions. The nature of these regions allows precise state to be reproduced by re-execution, obviating the need for hardware recovery support. We build upon the insight that programs naturally decompose into a series of idempotent regions and that these regions can be large. The paradigm of executing idempotent regions, which we call idempotent processing, can be used to support various types of speculation, including branch prediction, dependence prediction, or execution in the presence of hardware faults or exceptions.In this paper, we demonstrate how idempotent processing simplifies the design of in-order processors. Conventional in-order processors suffer from significant complexities to achieve high performance while supporting the execution of variable latency instructions and enforcing precise exceptions. Idempotent processing eliminates much of these complexities and the resulting inefficiencies by allowing instructions to retire out of order with support for re-execution when necessary to recover precise state. Across a diverse set of benchmark suites, our quantitative results show that we obtain a geometric mean performance increase of 4.4% (up to 25% and beyond) while maintaining an overall reduction in power and hardware complexity.

Static analysis and compiler design for idempotent processing

“…For exception recovery, Hampton and Asanović explore the use of idempotent regions for exception recovery in vector processors [16], De Kruijf and Sankaralingam use them for exception recovery in general purpose processors [10], and Mahlke et al propose restartable (idempotent) instruction sequences under sentinel scheduling for exception recovery in VLIW processors [23]. For fault recovery, Feng et al and De Kruijf et al both explore mechanisms to opportunistically employ idempotence over code regions that together cover large parts-but not all parts-of a program.…”

“…Table 1 classifies prior work in terms of its application domain and the level at which idempotence is used and identified [2,9,10,12,16,19,21,23,25,31,36]. One of the earliest uses is by Mahlke et al in using restartable instruction sequences for exception recovery in speculative processors [23].…”

iGPU: Exception support and speculative execution on GPUs

“…Again, others have made this observation as well [9,18,22]. However, they largely ignore live-state minimization and/or do not provide general exception and speculation support.…”

“…First, as shown in Figure 1(a), we observe that at each point in a program's execution there are differing amounts of live state. We build upon the observation previously made that programs fully decompose into idempotent (re-executable) code sequences [9], and partition GPU kernels into idempotent "regions" as shown in Figure 1(b), with the key property that the boundaries between regions fall at locations that contain relatively little amounts of live state. By their very nature, GPU application programs tend to have large regions of code that are idempotent and hence these regions can be very large (see Section 5).…”

“…To resolve the live-lock condition after it has been detected, previous work has proposed single-stepped reexecution for CPUs [9]. However, GPU single-stepped execution must occur at the granularity of individual SIMD lanes to allow precise servicing of individual exceptions.…”