Low-Cost Duplicate Multiplication

Sullivan, Michael; Swartzlander, Earl E.

doi:10.1109/arith.2015.29

Cited by 2 publications

(3 citation statements)

References 59 publications

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“…As there is no single/multiple error detecting BCD multiplier in the literature, we compare the proposed architectures with some state-of-the-art single/multiple error detecting non-BCD multipliers. The multipliers proposed in [36] are based on a general design for single error detection (SED) with the cost lower than a DMR. But the multipliers proposed in [35] either have single error detection or multiple error detection (MED) capability.…”

Section: Comparison With Other Designsmentioning

confidence: 99%

“…Since having both a low delay and a high multiple error detection is the main goal in this paper, these two parameters are compared with that of [35,36]. Fig.…”

Section: Comparison With Other Designsmentioning

confidence: 99%

“…Fig. 11 depicts the proposed self-checking 4-digit BCD multipliers in comparison with different types of single/multiple error detecting multipliers of [35,36] based on the delay overhead. According to Fig.…”

Section: Comparison With Other Designsmentioning

confidence: 99%

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High-speed binary coded decimal digit multipliers with multiple error detection

Yazdanian-Amiri,

Valinataj

2023

Integration

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Section: Comparison With Other Designsmentioning

confidence: 99%

“…Since having both a low delay and a high multiple error detection is the main goal in this paper, these two parameters are compared with that of [35,36]. Fig.…”

Section: Comparison With Other Designsmentioning

confidence: 99%

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High-speed binary coded decimal digit multipliers with multiple error detection

Yazdanian-Amiri,

Valinataj

2023

Integration

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High-speed binary coded decimal digit multipliers with multiple error detection

Yazdanian-Amiri

Valinataj

2023

Preprint

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Decimal arithmetic in the form of binary coded decimal (BCD) numbers is preferred in many financial and commercial applications. BCD multipliers are introduced as a key hardware unit to support both integer and floating-point decimal arithmetic operations. However, due to the increasing sensitivity of VLSI-based digital designs to the environmental effects, BCD multipliers are also prone to faults and errors similar to other arithmetic circuits. In addition, multiple error occurrence is possible in current digital systems which motivates to reach multiple error detection/correction in addition to single errors. In this paper, digit-by-digit BCD multipliers are introduced capable of multiple error detection with low delay overheads. To show the effectiveness of the proposed combined method, a 4-digit BCD multiplier is presented. Experimental results based on analysis and error injection-based simulations show that in addition to 100% single error detection, multiple errors can be detected with at least 99.6% probability in the 4-digit BCD multiplier as the implemented architecture.

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Low-Cost Duplicate Multiplication

Cited by 2 publications

References 59 publications

High-speed binary coded decimal digit multipliers with multiple error detection

High-speed binary coded decimal digit multipliers with multiple error detection

High-speed binary coded decimal digit multipliers with multiple error detection

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