iClaire: A Fast and General Layout Pattern Classification Algorithm With Clip Shifting and Centroid Recreation

Chang, Wei-Chun; Jiang, Iris Hui-Ru

doi:10.1109/tcad.2019.2917849

Cited by 7 publications

(6 citation statements)

References 24 publications

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“…In previous work [2,13,14], a few generic clustering algorithms such as k-means clustering [14], hierarchical and incremental clustering [2], and Markov clustering [13,15] were explored to solve this problem. In k-means clustering, the value of k needs to be provided by the user, but the user may not know the cluster count a priori.…”

Section: Overviewmentioning

confidence: 99%

CHIP: Clustering Hotspots in Layout Using Integer Programming

Takkala

Chu

2019

Journal of Electrical and Computer Engineering

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Clustering algorithms have been explored in recent years to solve hotspot clustering problems in integrated circuit design. With various applications in design for manufacturability flow such as hotspot library generation, systematic yield optimization, and design space exploration, generating good quality clusters along with their representative clips is of utmost importance. With several generic clustering algorithms at our disposal, hotspots can be clustered based on the distance metric defined while satisfying some tolerance conditions. However, the clusters generated from generic clustering algorithms need not achieve optimal results. In this paper, we introduce two optimal integer linear programming formulations based on triangle inequality to solve the problem of minimizing cluster count while satisfying given constraints. Apart from minimizing cluster count, we generate representative clips that best represent the clusters formed. We achieve a better cluster count for both formulations in most test cases as compared to the results published in the literature in the ICCAD 2016 contest benchmarks as well as the reference results reported in the ICCAD 2016 contest website.

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Section: Overviewmentioning

confidence: 99%

CHIP: Clustering Hotspots in Layout Using Integer Programming

Takkala

Chu

2019

Journal of Electrical and Computer Engineering

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“…2 shows a ML accelerated ILT mask synthesis flow. Related prior works include simple random sampling and geometrical pattern classification [1][2][3][4][5][6][7][8][9] , which generates geometrical representation of pattern clips in different forms and then forms groups by adopting different clustering algorithms. One full chip application 9 extracts a set of characteristic design patterns evenly distributed within the design space occupied by the layout sampling design, which is comprised of billions of patterns.…”

Section: Introductionmentioning

confidence: 99%

Automatic generation of representative and diversified pattern samples from a full chip layout

Zhu

Falch

Braam

et al. 2023

DTCO and Computational Patterning II

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To successfully transfer design patterns to wafer, it is essential to calibrate different types of models to describe the optical, physical, and chemical effects in chip manufacturing process. In recent years, there have also been active investigations of machine learning (ML) models to capture various aspects of semiconductor processes. As it is well known, model training time and model accuracy are heavily influenced by the input data. It is becoming increasingly important to provide highly efficient methods to automatically generate effective pattern samples from full chip designs. A straightforward approach, simple random sampling, can be highly efficient to generate effective samples for a homogeneous population. However, real world chip layouts are characterized by geometrical and lithographical feature distributions that vary significantly across the full chip design space. The complexity of the problem necessitates the adoption of a comprehensive set of approaches for sampling as well as flexibility in customizing the sampling strategy for various applications. In this paper, we investigate automatic layout sampling to optimize the coverage and diversity of patterns given the need for minimizing training sample size or other constraints, and therefore adopting various unsupervised learning techniques. The flow scales very well with computation resources to efficiently process full chip layouts. A simple, standard interface is provided for typical usage, but flexible programming APIs are available to customize the sampling strategy for advanced applications. Results demonstrate that the samples generated by this flow have increased diversity, which leads to significantly reduced model training time with comparable or increased model accuracy.

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“…Sometimes, the design hierarchy may be sub-optimal, containing very small cells and/or heavy overlap. When regarding utilizing the existing identical patterns for reduced runtime and better mask consistency, a straightforward approach is to leverage a pattern matching flow [5][6][7] , which requires the construction of a pattern library. The manual construction of this library is a formidable effort.…”

Section: Introductionmentioning

confidence: 99%

Scalable hierarchy extraction of repeating structures to enhance full chip mask synthesis

Zhu

Wang

Falch

et al. 2023

DTCO and Computational Patterning II

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For the past few decades, PPA (performance, power, and area) demand of computation infrastructure has been driving exponential increase of chip density. In recent years, the challenges of printability and process window for advanced manufacturing node continuously motivated innovations in reticle enhancement techniques, notably the adoption of inverse lithography technology (ILT) and curvilinear mask. We have observed a few challenges: 1) ILT provides unmatched quality of results but does incur additional computation time to manage; 2) for curvilinear mask, though the benefits are evident, the associated data volume is very large; and 3) mask consistency remains a critical component for design manufacturability. To utilize the advanced RET techniques to their full potential, it is crucial to identify the repeating structures in design layout and reuse the correction result, getting three benefits at the same time: reducing mask preparation runtime, reducing mask data volume, and improving mask consistency. Conventional layout repetition analysis is based on native design hierarchy. However, in many cases, the input layout for mask synthesis flows is either completely stripped of hierarchy or contains sub-optimal hierarchy. Some layout hierarchy can be detected and reconstructed using manual methods such as using user generated pattern library of highly repeating structures in conjunction with pattern matching technology. However, the preparation of such libraries is a formidable effort, and a significant number of repetitions in designs will be overlooked by this approach. In this paper, we investigate the automatic detection of repeating geometry structures and formed a hierarchy that is optimized for mask synthesis. The detection supports any process layer and both Manhattan and all-angle designs. The engine detects repeating regions of arbitrary shape. The detected repeating structures can also be applied within the chip or across chips to accelerate correction to further improve mask consistency. By scaling well to hundreds of processors, the distributed hierarchy extraction is very efficient for a full chip layout. For highly repetitive layouts, mask synthesis runtime reduction of more than an order of magnitude has been observed by performing this hierarchy extraction.

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iClaire: A Fast and General Layout Pattern Classification Algorithm With Clip Shifting and Centroid Recreation

Cited by 7 publications

References 24 publications

CHIP: Clustering Hotspots in Layout Using Integer Programming

CHIP: Clustering Hotspots in Layout Using Integer Programming

Automatic generation of representative and diversified pattern samples from a full chip layout

Scalable hierarchy extraction of repeating structures to enhance full chip mask synthesis

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