ICCAD-2013 CAD contest in mask optimization and benchmark suite

Abstract

Optical microlithography is the technique of printing a set of shapes on a wafer using light transmitted through a template called a mask. Repeatedly printing and stacking such shapes on top of each other to build electrical circuits allows us to manufacture chips in high volume. However this technique has now reached its fundamental physical limits of resolution. Current 193nm wavelength light is no longer sufficient to reliably transfer patterns which are now in the sub-100nm dimensional range. This has led to increased research in optimizing lithographic masks to pre-compensate for distortions introduced by the lithographic process. This is called mask optimization. In this contest, students are provided with a sample lithographic model which simulates the transfer of a mask pattern on to wafer. The mask is assumed to be a pixelated template, where every pixel can be turned on or off, to indicate where light passes through, or is blocked. Contestants are also provided with models to predict the robustness of their pattern i.e. how much variability is in the transferred pattern. Given these tools, the objective is to minimize the variability in the wafer image, as measured by process variability (PV) bands. This is subject to the constraints of runtime and satisfying pattern fidelity i.e. the transferred pattern should resemble the target pattern. Benchmarks are provided in the form of collections of geometric shapes, each of which provides a challenge in printing at sub-wavelength.

Optical Proximity Correction (OPC) Under Immersion Lithography

“…This is strictly subjected to the constraint that no additional EPE violations occur, as illustrated in Figure 17 in 1024  1024 pixels region, where each pixel represents 1 nm  1 nm. A set of 24 SOCS kernels forms the optical model in Lithosim [11].…”

“…The CD of those benchmarks ranges from 20 to 80 nm. The number of patterns (polygons) in those benchmarks ranges between 4 and 34 polygons with layout density ranges from 0.3 to 0.46 due to the pitch spacing design rules for realistic industrial cases [11].…”

“…The proposed algorithm in [16] has been compared with recently published algorithms executed on the same benchmarks. Table 1 shows a comparison between the proposed algorithm and state-of-the-art algorithms including: MOSAIC fast [36], MOSAIC exact [36], and PV-OPC [11].…”

“…Since finding an optimal mask solution with acceptable wafer image quality under all possible process conditions is infeasible, the industry defines a process window including a set of process conditions upon request. The most probable process condition is often defined as nominal process condition under which acceptable wafer image quality is desired with minimizing the variations between different images within the process window [10,11].…”

Triple patterning lithography (TPL) layout decomposition using end-cutting

“…4 present its simulated images through LELELE and LELE-EC processes, respectively. The lithography simulations are computed based on the partially coherent imaging system, where the 193nm illumination source is modeled as a kernel matrix given by [7]. To model the photoresist effect with the exposed light intensity, we use the constant threshold model with threshold 0.225.…”