IC power distribution challenges

Bobba, S.; Thorp, T.; Aingaran, K.; Liu, D.

doi:10.1109/iccad.2001.968729

Cited by 41 publications

(15 citation statements)

References 25 publications

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“…On the other hand, on-chip decaps are usually manufactured as gate capacitance of transistors. As the supply voltage continues scaling, leakage currents due to reduced threshold voltage and dielectric leakage prevent excessive use of decaps [3]. Thus, the economic use of onchip decaps is relatively important, especially in the presence of leakage current variations.…”

Section: Introductionmentioning

confidence: 99%

Voltage drop reduction for on-chip power delivery considering leakage current variations

Fan

Tan

2007

2007 25th International Conference on Computer Design

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Section: Introductionmentioning

confidence: 99%

Voltage drop reduction for on-chip power delivery considering leakage current variations

Fan

Tan

2007

2007 25th International Conference on Computer Design

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“…This condition becomes increasingly difficult to reach when the VLSI technology scaling results in increasing power supply noise on one hand and decreasing noise margins on the other hand. The power noise can be alleviated by placing on-chip decoupling capacitors (decap), which behave like local charge reservoirs to cushion any ditch or overshoot of power supply level [1]. However, imprudent usage of decap may cause exorbitant power dissipation, especially leakage power [2].…”

Section: Introductionmentioning

confidence: 99%

Fast Decap Allocation Based on Algebraic Multigrid

Zhuo¹,

Hu²,

Zhao³

et al. 2006

2006 IEEE/ACM International Conference on Computer Aided Design

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Decap (decoupling capacitor) is an effective technique for suppressing power supply noise. Nevertheless, over-usage of decap usually causes excessive power dissipation. Therefore, the total decap area needs to be minimized subject to power supply noise constraints. This is a complicated nonlinear optimization problem that may have as many as millions of variables. We propose an algebraic multigrid (AMG) based method to handle the high complexity. An error compensation scheme is developed to compensate the accuracy loss during the AMG reduction. A charge based back-mapping method and a few other techniques are suggested to further improve the computation efficiency. Our method is flexible to use and can be easily integrated with other existing decap allocation works. When compared to several previous works, the results from our method are usually the closest to the optimum. Our method also runs fast and can solve circuits with up to 1 million nodes in about 11 minutes. In addition, it has better scalability than the previous works.

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“…Problems, such as crosstalk, overshoot / undershoot (momentarily signal rising / decreasing above/below the power supply voltage (V DD ) and ground (V SS ) lines) [2] [3], reflection, electromagnetic interference -EMI, signal skew (delay in arrival time to different receivers) [4] [5] and power-supply noise [3] can lead to functional errors, which may cause yield loss (at the production stage) and/or dependability loss (during product lifetime). Both the power grid and the clock distribution network need to be carefully designed and tested [6].…”

Section: Introductionmentioning

confidence: 99%