IBM zEC12: The Third-Generation High-Frequency Mainframe Microprocessor

Shum, C-L Kevin; Busaba, F.Y.; Jacobi, Christian

doi:10.1109/mm.2013.9

Cited by 22 publications

(10 citation statements)

References 9 publications

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“…The introduction of the eDRAM in the cache introduces density, resulting in low leakage consumption. Shum et al [77] discuss an IBM zNext chip, which is a 3 rd Generation high frequency microprocessor chip. The chip has 6 cores instead of 4, dedicated-core core processors and a 48MB eDRAM on-chip shared L3.…”

Section: Energy Saving Chipsmentioning

confidence: 99%

A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption

Bhebhe

Agyeman

2016

CAE

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Abstract-The search goes on for another ground breaking phenomenon to reduce the ever-increasing disparity between the CPU performance and storage. There are encouraging breakthroughs in enhancing CPU performance through fabrication technologies and changes in chip designs but not as much luck has been struck with regards to the computer storage resulting in material negative system performance. A lot of research effort has been put on finding techniques that can improve the energy efficiency of cache architectures. This work is a survey of energy saving techniques which are grouped on whether they save the dynamic energy, leakage energy or both. Needless to mention, the aim of this work is to compile a quick reference guide of energy saving techniques from 2013 to 2016 for engineers, researchers and students.

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Section: Energy Saving Chipsmentioning

confidence: 99%

A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption

Bhebhe

Agyeman

2016

CAE

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“…The main components of the branch prediction logic are similar to those in the zEC12 processor [4], but there have been changes in their sizes and configurations (see Table 2). The first-level Branch Target Buffer (BTB1) is indexed and tagged with the virtual instruction address, and each BTB1 entry provides branch target address predictions.…”

Section: Branch Prediction and Instruction Fetchingmentioning

confidence: 99%

“…Since re-indexing of the search process now only occurs after predicted-taken branches, the 64-entry fast index table (FIT) [4] has been replaced with a 1,024-entry BTB1 column predictor (CPRED) that enables a fastest prediction rate of one taken branch every two cycles, the same as that provided by the FIT on the prior machine. The CPRED works by predicting for each search whether there will be a taken prediction from the BTB1, and if so, from which column.…”

Section: Branch Prediction and Instruction Fetchingmentioning

confidence: 99%

“…This mainframe microprocessor design has evolved in multiple dimensions, including frequency, pipeline depth, branch prediction, superscalar/instruction level parallelism, out-of-order execution, and multithreading. The z13 builds upon the out-of-order execution base introduced on the IBM zEnterprise* 196 (z196) [2,3], and its performance gains are achieved relative to that design and its successorVthe IBM zEC12 system [4]Vin both single-thread (single code stream) and in total system-level throughput. The single-thread performance gains are predominately achieved by major advancements in branch prediction throughput; higher instruction decode, dispatch, and completion rates; larger fixed point and floating point execution bandwidth; larger caches; and larger out-of-order execution windows.…”

Section: Introductionmentioning

confidence: 99%

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The IBM z13 multithreaded microprocessor

et al. 2015

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The IBM z13i system is the latest generation of the IBM z Systemsi mainframes. The z13 microprocessor improves upon the IBM zEnterprise A EC12 (zEC12) processor with two vector execution units, higher instruction execution parallelism, and a simultaneous multithreaded (SMT) architecture that supports concurrent execution of two threads. These advances yield performance gains in legacy online transaction processing and business analytics workloads. This latest generation system features an eight-core processor chip, a robust cache hierarchy, and large multiprocessor system design optimized for enterprise database and transaction processing workloads. The microprocessor core features a wide super-scalar, out-of-order pipeline that can sustain an instruction fetch, decode, dispatch, and completion rate of six z/Architecture A instructions per cycle. The instruction execution path is predicted by multi-level branch direction and target prediction logic. Complex instructions are split into two or more simpler micro-operations. Instructions are issued out of program order from an instruction issue queue to multiple RISC (reduced instruction set computer) execution units. The super-scalar design can sustain an issue and execution rate of ten micro-operations per cycle: two load/store type instructions, four fixed point (integer) instructions, two floating point or vector instructions, and two branch instructions.

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“…With the introduction of the z13 architecture, the emphasis is on increasing performance while increasing power-efficiency through new architectural facilities that exploit application parallelism. To improve power-efficiency, the z13 processor operates at a reduced, more power-efficient, operating frequency of 5 GHz (dropping the frequency by approximately 10% from the 5.5-GHz IBM Enterprise [zEC12] processor [11]). To offset the reduced frequency and deliver overall performance growth, performance gains are achieved instead by CPI reduction and parallelism.…”

Section: Figurementioning

confidence: 99%

The SIMD accelerator for business analytics on the IBM z13

et al. 2015

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I. M. Nnebe M. Gschwind IBM z Systemsi have been hosting critical business applications across several industries including banking, healthcare, insurance, and retail for over 50 years. With the recent growth in the use of analytics in the business environment, more customers are seeking to integrate analytics into their core operational environments to enable real-time insight on operational data for competitive advantage. IBM z Systems support very high-performance computation for business analytics. The z System processors are typically higher frequency than any general-purpose microprocessor, and with the zEnterprise A 196 (z196) system, huge gains in performance were made through out-of-order execution. The robust cache hierarchy also provides additional performance boosts to high concurrency analytics operations. The IBM z13i extends these performance improvements with a new SIMD (single-instruction, multiple-data) engine in the processor for targeted acceleration of business analytics workloads. This SIMD engine supports new instructions for three data types: integer, string, and floating-point. We provide an overview of the z13 SIMD architecture and show how it advances current architectures. We also discuss the compiler and math library support for this new architecture and provide a few examples of applications that can be accelerated by this new hardware feature on the z13.

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IBM zEC12: The Third-Generation High-Frequency Mainframe Microprocessor

Cited by 22 publications

References 9 publications

A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption

A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption

The IBM z13 multithreaded microprocessor

The SIMD accelerator for business analytics on the IBM z13

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