IBM POWER7 multicore server processor

Sinharoy, Balaram; Kalla, R.; Starke, William J.; Le, H. Q.; Cargnoni, R.; Norstrand, J. A. Van; Ronchetti, B. J.; Stuecheli, Jeffrey; Leenstra, J.; Guthrie, Guy L.; Nguyen, D. Q.; Blaner, B.; Marino, Charles F.; Retter, E.; Williams, Peter

doi:10.1147/jrd.2011.2127330

Cited by 133 publications

(116 citation statements)

References 12 publications

(18 reference statements)

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“…The DV F S chip column is generated using Equation 1 that defines the number of models needed when the DVFS mechanism is implemented globally, in which all cores in the chip share the same DVFS state, like in the Intel R Core TM 2 processor [32]. In contrast, the DV F S core column, generated using the Equation 2, 2 3 6 9 2 18 36 189 8 3 24 164 8 18 144 1562274 16 3 48 968 16 18 288 2203961429 shows the number of models needed if per core DVFS is implemented, in which each core can run at a different DVFS state 3 , like in the POWER7 processor [33].…”

Section: Motivationmentioning

confidence: 99%

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Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up

Bertran

González

Martorell

et al. 2012

The Computer Journal

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Counter-based power models have attracted the interest of researchers because they became a quick approach to know the insights of power consumption. Moreover, they allow to overpass the limitations of measurement devices. In this paper, we compare different Top-down and Bottom-up Counter-based modeling methods. We present a qualitative and quantitative evaluation of their properties. In addition, we study how to extend them to support the currently ubiquitous Dynamic Voltage and Frequency Scaling (DVFS) mechanism. We propose a simple method to generate DVFS agnostic power models from the DVFS specific models. The proposed method is applicable to models generated using any methodology and allows the reduction of the modeling time without affecting the fundamental properties of the models. The study is performed on an 18 DVFS states Intel R Core TM 2 platform using the SPECcpu2006, NAS and LMBENCH benchmark suites. In our testbed, a 6x reduction on the modeling time only increments 1 percentage point on average the error in the predictions.

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Section: Motivationmentioning

confidence: 99%

“…Moreover, on current architectures the DVFS is not applied homogeneously among all the microarchitectural components [33]. As a result, directly scaling the models would affect their properties.…”

Section: Dvfs Agnostic Power Modelsmentioning

confidence: 99%

Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up

Bertran

González

Martorell

et al. 2012

The Computer Journal

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show abstract

“…The primary factor behind this improvement is an increase in the width of cores. Recently, 8-issue cores, such as the IBM POWER8, and Intel Haswell and Skylake, have come onto the market [3]- [6].…”

Section: Introductionmentioning

confidence: 99%

Skewed Multistaged Multibanked Register File for Area and Energy Efficiency

Yamada

Jimbo

Shioya

et al. 2017

IEICE Trans. Inf. & Syst.

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SUMMARYThe region that includes the register file is a hot spot in high-performance cores that limits the clock frequency. Although multibanking drastically reduces the area and energy consumption of the register files of superscalar processor cores, it suffers from low IPC due to bank conflicts. Our skewed multistaging drastically reduces not the bank conflict probability but the pipeline disturbance probability by the second stage. The evaluation results show that, compared with NORCS, which is the latest research on a register file for area and energy efficiency, a proposed register file with 18 banks achieves a 39.9% and 66.4% reduction in circuit area and in energy consumption, while maintaining a relative IPC of 97.5%.

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“…In contrast, in embedded Dynamic RAM (eDRAM) cells, which have been also used in some modern processors [8], errors basically lump into the cell retention time instead of altering the stored value. The worst case of these device variations determines the refresh period for the whole eDRAM array.…”

Section: Introductionmentioning

confidence: 99%

Enhancing Performance and Energy Consumption of HER Caches by Adding Associativity

Lorente

Valero

Canal

2014

Euro-Par 2013: Parallel Processing Workshops

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Abstract. Unlike other previous techniques, the recently proposed Hard Error Recovery (HER) fault-tolerant cache provides 100% fault-coverage in L1 data caches. This full coverage makes the HER cache appropiate for fault-dominated future technology nodes. An n-way set-associative HER cache implements one cache way with fast SRAM banks and the remaining ways with eDRAM banks to address power and area. Since the number of eDRAM cache blocks used in a specific HER cache organization depends on the cache associativity (i.e., the implemented number of ways), we expect that the performance and energy consumption provided by a given HER cache design strongly depends on the cache geometry. In this work we study the behavior of the HER cache design when applied to a highly associative L1 cache like those found in some modern microprocessors. In particular this work explores a 32KB 8-way associative L1 data cache such as the one used in Intel Haswell microarchitecture. Experimental results show that, at low-power modes compared to a conventional cache with the same storage capacity and number of ways, area, leakage power, and dynamic energy savings of a 4-way HER cache are by 25%, 85%, and 62%, respectively. These percentages are further improved (by 40%, 89%, and 68%, respectively) when the cache associativity is increased to 8 ways, while the performance loss with respect to both an 8-way conventional cache and the 4-way HER cache is minimal.

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IBM POWER7 multicore server processor

Cited by 133 publications

References 12 publications

Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up

Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up

Skewed Multistaged Multibanked Register File for Area and Energy Efficiency

Enhancing Performance and Energy Consumption of HER Caches by Adding Associativity

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