IBM POWER6 accelerators: VMX and DFU

Abstract

The IBM POWER6e microprocessor core includes two accelerators for increasing performance of specific workloads. The vector multimedia extension (VMX) provides a vector acceleration of graphic and scientific workloads. It provides single instructions that work on multiple data elements. The instructions separate a 128-bit vector into different components that are operated on concurrently. The decimal floating-point unit (DFU) provides acceleration of commercial workloads, more specifically, financial transactions. It provides a new number system that performs implicit rounding to decimal radix points, a feature essential to monetary transactions. The IBM POWERe processor instruction set is substantially expanded with the addition of these two accelerators. The VMX architecture contains 176 instructions, while the DFU architecture adds 54 instructions to the base architecture. The IEEE 754R Binary Floating-Point Arithmetic Standard defines decimal floating-point formats, and the POWER6 processor-on which a substantial amount of area has been devoted to increasing performance of both scientific and commercial workloads-is the first commercial hardware implementation of this format.

FPGA implementation of decimal processors for hardware acceleration

“…However, software operations run 100-1000 times slower than the corresponding binary operations implemented in hardware. For these reasons, in the revised IEEE standard 754 [5] support for decimal representation was added, and some companies are already commercializing processors which include decimal units [6], [7]. In this work, we show that we can accelerate with a decimal processor implemented on FPGA the accounting typically done by telephone companies.…”

Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs

“…IBM has responded to this market demand and integrates decimal floating-point arithmetic in recent processor architectures such as z9 [6], z10 [7], Power6 [8], and Power7 [9]. The Power6 is the first microprocessor that implements IEEE 754-2008 decimal floating-point format fully in hardware, while the earlier released z9 already supports decimal floating-point operations but implements them mainly in millicode.…”

Design and implementation of a Radix-100 division unit

“…Until now, full IEEE 754-2008 supportive DFUs were limited on some certain highend microprocessors [4], for example, IBM POWER6 [5], IBM mainframe Z9 (with assistance) [6], and IBM mainframe Z10 [7], while in most other microprocessors, decimal operations were based on software libraries or integer decimal arithmetic units (IBM Z900 [8]). …”