In Situ Current-Accelerated Phase Cycling with Metallic and Semiconducting Switching in Copper Nanobelts at Room Temperature

Abstract

Here, a current-accelerated phase cycling by an in situ current-induced oxidation process was demonstrated to reversibly switch the local metallic Cu and semiconducting Cu 2 O phases of patterned polycrystalline copper nanobelts. Once the Cu nanobelts were applied by a direct-current bias of ∼0.5 to 1 V in air with opposite polarities, the resistance between several hundred ohms and more than MΩ can be manipulated. In practice, the thickness of 60 nm with a moderate grain size inhibiting both electromigration and permanent oxidation is the optimized condition for reversible switching when the oxygen supply is sufficient. More than 40% of the copper localized beneath the positively biased electrode was oxidized assisted by the Joule heating, blocking the current flow. On the contrary, the reduction reaction of Cu 2 O was activated by the thermally assisted electromigration of Cu atoms penetrating the interlayer at the reverse bias. Finally, based on a high on/off ratio, the fast switching and the scalable production, reusable feasibility based on copper nanobelts such as the memristor array was demonstrated.

Stable Resistance Switching in Lu3N@C80 Nanowires Promoted by the Endohedral Effect: Implications for Single-Fullerene Motion Resistance Switching

“…The results revealed a clear correlation between the extent of EB irradiation and the conductivity of the C 60 NWs . Similar resistance switching has been reported in other crystals and is expected to be applied to nanoelectronics. − Two-terminal devices with source and drain are expected to find application in single-fullerene motion resistive switching and nonvolatile memory. ,, …”

“…37−40 Two-terminal devices with source and drain are expected to find application in single-fullerene motion resistive switching and nonvolatile memory. 37,38,41 In the present report, we explored the electrical properties of Lu 3 N@C 80 NWs (Lu 3 N@C 80 NWs) for advanced conduction control. Lu 3 N@C 80 is an endohedral fullerene composed of Lu 3 N inside a C 80 cage.…”

Solid-Ionic Memory in a van der Waals Heterostructure

“…The electronic properties of atom-thin 2D materials are sensitive to defect states intrinsically or adjacently. But there were few reported effective approaches to reversibly manipulate defect states for controlling carrier densities in 2D materials, most of which still suffer from poor stability, critical operation conditions, and high energy consumptions. , Solid-ionic gating is one of the recent trending methods to locally modulate carrier concentrations in low-dimensional semiconductors, which can dope channels with electromigration. , Compared to traditional liquid-ionic gating, solid-ionic gating can accomplish local doping and efficiently exclude the risk of unexpected surface reactions, providing a precise and stable modulation on the active channel area. However, solid-ionic gating materials explored so far are usually limited by demanding temperature conditions and single-mode operation (electricity), which constrains the programming/erasing speeds and their applications in integrated circuits. , For instance, AgI was recently reported as an efficient solid-ionic layer for electrostatically doping WSe 2 channels, but different temperatures were required for programming and operating, and further environment cues were also needed to erase the programmed functions …”

“…2,3 Solid-ionic gating is one of the recent trending methods to locally modulate carrier concentrations in low-dimensional semiconductors, which can dope channels with electromigration. 4,5 Compared to traditional liquid-ionic gating, solid-ionic gating can accomplish local doping and efficiently exclude the risk of unexpected surface reactions, 6 providing a precise and stable modulation on the active channel area. However, solid-ionic gating materials explored so far are usually limited by demanding temperature conditions and single-mode operation (electricity), which constrains the programming/erasing speeds and their applications in integrated circuits.…”