Hysteresis in the resistance of a graphene device induced by charge modulation in the substrate

Brant, J. C.; Leon, J.; Barbosa, Tiago Campolina; Araújo, Eduardo Nery Duarte de; Archanjo, Bráulio S.; Plentz, F.; Alves, Endrigo Gabellini Leonel

doi:10.1063/1.3473815

Cited by 21 publications

(10 citation statements)

References 15 publications

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“…Device‐to‐device variation of Δ V Dirac was much smaller in the DT‐graphene FETs as well. The effective suppression of hysteresis in the DT‐graphene FET originates from the absence of charge‐trapping sites, i.e., ionic and metal residues at the graphene/substrate interface . In addition, the DT‐graphene FETs exhibited enhanced electron‐current modulation and a resulting improvement of symmetry in charge‐carrier transport as compared to the WT‐graphene FETs (Figure c and f).…”

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confidence: 97%

Metal-Etching-Free Direct Delamination and Transfer of Single-Layer Graphene with a High Degree of Freedom

Yang

Jung

et al. 2014

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A method of graphene transfer without metal etching is developed to minimize the contamination of graphene in the transfer process and to endow the transfer process with a greater degree of freedom. The method involves direct delamination of single-layer graphene from a growth substrate, resulting in transferred graphene with nearly zero Dirac voltage due to the absence of residues that would originate from metal etching. Several demonstrations are also presented to show the high degree of freedom and the resulting versatility of this transfer method.

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confidence: 97%

Metal-Etching-Free Direct Delamination and Transfer of Single-Layer Graphene with a High Degree of Freedom

Yang

Jung

et al. 2014

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“…Graphene has attracted tremendous interest due to its unique electronic structure, ultrahigh mobility, and near ballistic transport characteristics. − Although the Fermi level of intrinsic graphene is expected to be at the Dirac point, recent electrical transport measurements often showed that most of the graphene transistors on SiO 2 substrates in air were p-doped. , When constructing combinatorial logic circuits, control of the carrier density in graphene, to realize both n- and p-type conductive channels, is desired. In silicon-based field effect transistors (FETs), ion implantation is a reliable method of carrier doping in the active channel. , However, the technique is not applicable to graphene because it will destroy the two-dimensional carbon structure.…”

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confidence: 99%

Control of Carrier Type and Density in Exfoliated Graphene by Interface Engineering

et al. 2010

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Air-stable, n-doped or p-doped graphene sheets on a chip were achieved by modifying the substrates with self-assembled layers of silane and polymer. The interfacial effects on the electronic properties of graphene were investigated using micro-Raman and Kelvin probe force microscopy (KPFM). Raman studies demonstrated that the phonon vibrations were sensitive to the doping level of graphene on the various substrates. Complementary information on the charge transfer between the graphene and substrate was extracted by measuring the surface potential of graphene flakes using KPFM, which illustrated the distribution of carriers in different graphene layers as well as the formation of dipoles at the interface. The Fermi level of single layer graphene on the modified substrates could be tuned in a range from -130 to 90 mV with respect to the Dirac point, corresponding to the doped carrier concentrations up to 10(12) cm(-2).

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“…The C−V characteristics at 95 K for different frequencies (Figure 2b) show that the device does not go to the inversion region in the negative gate voltage and it rather goes into the deep depletion due to the nonavailability of minority carriers as a result of the carrier freezing out. 25 Moreover, the spread in the C−V curves is reduced by varying the frequencies, indicating the reduction in the interfacial trapping−detrapping processes at low temperature. 37,40 To get further insights into the transport behavior of the graphene field-effect transistor, we investigated the lowfrequency resistance fluctuations or noise of the device by varying the gate voltage and temperature.…”

Section: ■ Results and Discussionmentioning

confidence: 99%

“…In the positive side (accumulation region), resistance decreases with temperature at all gate voltages, indicating metallic behavior. The C-V characteristics at 95 K for different frequencies (Figure 2b) show that the device does not go to the inversion region in the negative gate voltage, rather goes into the deep depletion due to the non-availability of minority carriers as a result of carrier freeze out 25 . Moreover, the spread in the C-V curves is reduced by varying the frequencies, indicating that the reduction in the interfacial trapping-detrapping processes at low temperature 37,40 .…”

Section: Resultsmentioning

confidence: 99%

Sensing Remote Bulk Defects through Resistance Noise in a Large-Area Graphene Field-Effect Transistor

Shubhadip

Alam

Pal

2022

ACS Appl. Mater. Interfaces

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Substrate plays a crucial role in determining transport and low frequency noise behavior of graphene field effect devices. Typically, heavily dope Si/SiO2 substrate is used to fabricate these devices for efficient gating. Trapping-detrapping processes closed to the graphene/substrate interface are the dominant sources of resistance fluctuations in the graphene channel, while Coulomb fluctuations arising due to any remote charge fluctuations inside the bulk of the substrate are effectively screened by the heavily doped substrate. Here, we present electronic transport and low frequency noise characteristics of large area CVD graphene field effect transistor (FET) prepared on a lightly doped Si/SiO2 substrate (NA ≈ 10 15 cm -3 ). Through a systematic characterization of transport, noise and capacitance at various temperature, we reveal that remote Si/SiO2 interface can affect the charge transport in graphene severely and any charge fluctuations inside bulk of the silicon substrate can be sensed by the graphene channel. The resistance (R) vs. back gate voltage (Vbg) characteristics of the device shows a hump around the depletion region formed at the SiO2/Si interface, confirmed by the capacitance (C) -Voltage (V) measurement. Low frequency noise measurement on these fabricated devices shows a peak in the noise amplitude close to the depletion region. This indicates that due to the absence of any charge layer at Si/SiO2 interface, screening ability decreases and as a consequence, any fluctuations in the deep level coulomb impurities inside the silicon substrate can be observed as a noise in resistance in graphene channel via mobility fluctuations. Noise behavior on ionic liquid gated graphene on the same substrate exhibits no such peak in noise and can be explained by the interfacial trappingdetrapping processes closed to the graphene channel. Our study will definitely be useful for integrating graphene with the existing silicon technology, in particular, for high frequency applications.

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Hysteresis in the resistance of a graphene device induced by charge modulation in the substrate

Cited by 21 publications

References 15 publications

Metal-Etching-Free Direct Delamination and Transfer of Single-Layer Graphene with a High Degree of Freedom

Metal-Etching-Free Direct Delamination and Transfer of Single-Layer Graphene with a High Degree of Freedom

Control of Carrier Type and Density in Exfoliated Graphene by Interface Engineering

Sensing Remote Bulk Defects through Resistance Noise in a Large-Area Graphene Field-Effect Transistor

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