2010
DOI: 10.1021/nn102236x
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Control of Carrier Type and Density in Exfoliated Graphene by Interface Engineering

Abstract: Air-stable, n-doped or p-doped graphene sheets on a chip were achieved by modifying the substrates with self-assembled layers of silane and polymer. The interfacial effects on the electronic properties of graphene were investigated using micro-Raman and Kelvin probe force microscopy (KPFM). Raman studies demonstrated that the phonon vibrations were sensitive to the doping level of graphene on the various substrates. Complementary information on the charge transfer between the graphene and substrate was extract… Show more

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Cited by 128 publications
(126 citation statements)
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“…This hypothesis is also confirmed by the change in slope of the 52˚C acid temperature line in figure 1f after the annealing at 200 ˚C, in agreement with previous results. It is worth noting that, even though the monolayer-graphene sheet resistance in this work is comparable with the lowest reported to date, 8 it may be possible to further reduce this value by changing or pretreating the substrate 41,42,43 or by modifying the CVD graphene quality.…”
Section: Discussionsupporting
confidence: 62%
“…This hypothesis is also confirmed by the change in slope of the 52˚C acid temperature line in figure 1f after the annealing at 200 ˚C, in agreement with previous results. It is worth noting that, even though the monolayer-graphene sheet resistance in this work is comparable with the lowest reported to date, 8 it may be possible to further reduce this value by changing or pretreating the substrate 41,42,43 or by modifying the CVD graphene quality.…”
Section: Discussionsupporting
confidence: 62%
“…According to some previous reports, theoretical limit of sheet carrier density in the case of single layer has approached ∼10 12 cm −2 . 21 This limit is expected due to the fact that the sheet carrier density is in principle, obtained by multiplying the film thickness to the bulk carrier density. 7 However, recently in doped graphene high sheet carrier concentration n ≈ 10 15 cm −2 have been reported suggesting a Fermi level pinning far apart from the Dirac point, depending on the type of carrier.…”
Section: Simulation Structurementioning
confidence: 99%
“…In this work, the slight differences in the mobility of graphene and PEIE coated graphene FET devices can be due to the differences in the transferred graphene that has origins in varying grain size or transfer process of CVD graphene. [ 60,61 ] [ 62 ] This is due to the chirality of the massless Dirac fermions of graphene, which suppresses backscattering by potential barriers (Klein Tunneling). [7] The PEIE thickness on the substrate can be tuned to fully control the transport behavior of the fabricated p-n-p junction.…”
Section: Electrical Data Measurementsmentioning
confidence: 99%