Hysteresis-free organic field-effect transistors and inverters using photocrosslinkable poly(vinyl cinnamate) as a gate dielectric

Abstract

We have fabricated organic field-effect transistors (OFETs) and inverters using photocrosslinkable poly(vinyl cinnamate) (PVCN) as a gate dielectric. The photocrosslinked PVCN dielectric film has superior insulating properties and does not require thermal curing. The high water resistance of the dielectric, which arises because PVCN is hydroxyl group-free, means that the devices were found to be hysteresis-free in all operations. The OFETs with the PVCN dielectric were found to exhibit a carrier mobility of 0.51cm2∕Vs, an on/off ratio of 106, and a subthreshold swing of 0.913V/decade. An organic inverter consisting of two OFETs exhibited a high inverter gain of 17.9.

Air-stable n-type organic thin-film transistor array and high gain complementary inverter on flexible substrate

“…In particular, low-k and hydrophobic polymer gate dielectrics, which do not contain hydroxyl groups, are known to offer stable and hysteresis-free OTFT operation. 11,13 Excellent transistor performances with polymer gate dielectrics, such as cross-linkable poly͑4-vinylphenol͒ 14,15 and amorphous fluoropolymer, [16][17][18] have been reported.…”

Integration of a Low-Voltage Organic Field-Effect Transistor and a Sensing Capacitor for a Pressure-Sensing Device

“…Figure 2 (a) shows an atomic force microscope (AFM) image of the PVC gate dielectric surface. The film was found to have a very smooth and pinhole-free surface, with a rootmean square roughness of 0.20 nm within a 5 × 5 µm 2 scan scale, which is much smoother than the value (0.67 nm) for the of PVC film previously reported [8]. Figure 2 (b) shows a polarized microscope image of the TIPS-pentacene/PS active layer.…”

Fabrication of n‐ and p‐Type Organic Thin Film Transistors with Minimized Gate Overlaps by Self‐Aligned Nanoimprinting

“…The on/off ratio of the transistor is 10 4 . Note the small gate leakage current I GS not exceeding 10 pA up to gate voltages of 20 V. This corresponds to a breakdown field of about 3 MV/cm which is remarkably high for polymer dielectrics 23–25. We attribute this finding to the small gate to source/drain overlap areas inherent to self‐aligned transistors thus resulting in a decreased number of area‐related defects in the dielectric and therefore decreasing the probability for breakthrough underneath the contacts.…”