Based on the powerful concept of embedded dipole self‐assembled monolayers (SAMs), highly conductive interfacial layers are designed, which allow tuning the contact resistance of organic thin‐film transistors over three orders of magnitude with minimum values well below 1 kΩ cm. This not only permits the realization of highly competitive p‐type (pentacene‐based) devices on rigid as well as flexible substrates, but also enables the realization of n‐type (C60‐based) transistors with comparable characteristics utilizing the same electrode material (Au). As prototypical examples for the high potential of the presented SAMs in more complex device structures, flexible organic inverters with static gains of 220 V/V and a 5‐stage ring‐oscillator operated below 4 V with a stage frequency in the range of the theoretically achievable maximum are fabricated. Employing a variety of complementary experimental and modeling techniques, it is shown that contact resistances are reduced by i) eliminating the injection barrier through a suitable dipole orientation, and by ii) boosting the transmission of charge carriers through a deliberate reduction of the SAM thickness. Notably, the embedding of the dipolar group into the backbones of the SAM‐forming molecules allows exploiting their beneficial effects without modifying the growth of the active layer.

In this study we report on the optimization of the contact resistance by surface treatment in short‐channel bottom‐contact OTFTs based on pentacene as semiconductor and SiO2 as gate dielectric. The devices have been fabricated by means of nanoimprint lithography with channel lengths in the range of 0.3 μm < L < 3.0 μm. In order to reduce the contact resistance the Au source‐ and drain‐contacts were subjected to a special UV/ozone treatment, which induced the formation of a thin AuOx layer. It turned out, that the treatment is very effective (i) in decreasing the hole‐injection barrier between Au and pentacene and (ii) in improving the morphology of pentacene on top of the Au contacts and thus reducing the access resistance of carriers to the channel. Contact resistance values as low as 80 Ω cm were achieved for gate voltages well above the threshold. In devices with untreated contacts, the charge carrier mobility shows a power‐law dependence on the channel length, which is closely related to the contact resistance and to the grain‐size of the pentacene crystallites. Devices with UV/ozone treated contacts of very low resistance, however, exhibit a charge carrier mobility in the range of 0.3 cm2 V–1 s–1 < μ < 0.4 cm2 V–1 s–1 independent of the channel length.

We report on the natural source based and biodegradable material cellulose on Al2O3 as ultrathin hybrid high-k dielectric layer for applications in green electronics. Dielectric films of 16 nm cellulose (ε ≈ 8.4) and 8 nm Al2O3 (ε ≈ 9) exhibit low leakage currents up to electric fields of 1.5 MV/cm. Pentacene and C60 based organic thin film transistors show a well-balanced performance with operation voltages around 2 V. They are implemented in complementary inverters with excellent switching behavior, a small-signal gain up to 60 and with exceptionally high and balanced noise margin values of 82% at ultralow operation voltage (VDD = 2.5 V).

A nanoimprinting process that enables fabrication of self‐aligned p‐ and n‐type organic thin film transistors with small channel lengths is presented. Nanoimprint lithography with back‐side exposure permit precise definition of the channel length down to the submicrometer regime and a diminutive gate to source/drain overlap. The self‐aligned manufacturing process enables transistor setups with minimized electrode overlaps resulting in distinct decrease of parasitic capacitances and considerable increase in transition frequency. Fully functional small channel OTFTs with p‐ and n‐type semiconductors are fabricated on glass as well as on flexible substrates with transition frequencies up to 400 kHz.

Bottom‐contact architectures with common electrode materials such as gold are crucial for the integration of 2D semiconductors into existing device concepts. The high contact resistance to gold—especially for bottom contacts—is, however, a general problem in 2D semiconductor thin‐film transistors. Pyrimidine‐containing self‐assembled monolayers on gold electrodes are investigated for tuning the electrode work functions in order to minimize that contact resistance. Their frequently ignored asymmetric and bias‐dependent nature is recorded by Kelvin probe force microscopy through a direct mapping of the potential drop across the channel during device operation. A reduction of the contact resistances exceeding two orders of magnitude is achieved via a suitable self‐assembled monolayer, which vastly improves the overall device performance.

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The processing of complex nanoscale electronic structures on plastic substrates is a significant challenge, requiring the combination of low temperature, nonaggressive, and high resolution methods. Here a scalable process flow on plastic is presented tbat enables the fabrication of flexible nano­imprinted organic field‐effect transistors (OFETs) with self‐aligned contacts and solution‐processed semiconductor and dielectric layers, at processing temperatures ≤ 150 °C. OFETs are fabricated with device cutoff frequencies f > 1 MHz at low operating bias V DS = −15 V. The technique allows the patterning of metal structures over four orders of magnitude from 375 nm to 1 mm without the need for a rigid carrier, and provides a fabrication pathway to high performance nanostructured organic circuitry.

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