HyPHI - Task Based Hybrid Execution C++ Library for the Intel Xeon Phi Coprocessor

Dokulil, Jiri; Bajrovic, Enes; Benkner, Siegfried; Sandrieser, Martin; Bachmayer, Beverly

doi:10.1109/icpp.2013.37

Cited by 11 publications

(6 citation statements)

References 6 publications

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“…The HyPHI library leverages the similarity of the Xeon Phi architecture (compared to the standard x86-64 architecture) to allow hybrid execution with a single source code utilizing all cores of the host processor(s) and coprocessor(s) simultaneously. Our previous experiments have shown that such hybrid execution allows us to better exploit systems equipped with coprocessors and get closer to their full potential [4], [6]. The outer for-loop is a time step loop, which is a common pattern for many simulation codes.…”

Section: Hyphi Librarymentioning

confidence: 98%

“…One established way to tackle the high programming complexity is the use of welldefined parallel programming patterns. This methodology has already been applied successfully by various libraries targeting accelerated parallel systems (e.g., Thrust [1], SkePU [2], PEP-PHER [3], HyPHI [4]). However, even though parallel pattern programming libraries may significantly improve programmability, an efficient and portable implementation of such libraries is challenging.…”

Section: Introductionmentioning

confidence: 99%

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Automatic Tuning of a Parallel Pattern Library for Heterogeneous Systems with Intel Xeon Phi

Dokulil

Benkner

2014

2014 IEEE International Symposium on Parallel and Distributed Processing With Applications

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Pattern libraries are important tools for high productivity application development. Their struggle for best performance is complicated by the fact that they are used to execute user-provided code, which is not known during their creation. This makes pattern libraries good candidate for automatic software tuning. In this paper, we deal with automatic online parameter tuning of the HyPHI hybrid pattern library for heterogeneous systems equipped with the Intel Xeon Phi coprocessors. We propose a framework that can be used to combine a pattern library with an existing tuning library in a practical and efficient way. Our experiments show that tuning can noticeably improve the performance of the library and it introduces very little overhead.

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Section: Hyphi Librarymentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

Automatic Tuning of a Parallel Pattern Library for Heterogeneous Systems with Intel Xeon Phi

Dokulil

Benkner

2014

2014 IEEE International Symposium on Parallel and Distributed Processing With Applications

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“…In the HyPHI project [13], we have built a pattern library for the Intel Xeon Phi coprocessor. However, the library is based on an offload programming model that provides full bi-directional communication between the host and the coprocessor.…”

Section: Related Workmentioning

confidence: 99%

Towards High-Level Parallel Patterns in OpenCL

Dokulil

Benkner

2014

2014 15th International Conference on Parallel and Distributed Computing, Applications and Technologies

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Parallel pattern libraries (e.g., Intel TBB) are popular and useful tools for developing applications in SMP environments at a higher level of abstraction. Such libraries execute user-provided code efficiently on shared memory parallel architectures in accordance with well-defined execution patterns like parallel for-loops or pipelines. For heterogeneous architectures comprised of CPUs and accelerators, OpenCL has gained a lot of momentum. Since accelerated architectures do not provide a shared memory, it is not possible to directly use the approach taken in pattern libraries for SMP systems for OpenCL as well. In this paper, we are exploring issues and opportunities encountered by attempts to provide such patterns in the context of OpenCL. Based on a set of experiments with a scientific application on diverse OpenCL devices, we point out major pitfalls and insights, and outline directions for further efforts in developing pattern libraries for OpenCL.

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“…Particularly, such a large number of threads can lead to a significant amount of contention if the execution involves frequent locking operations. Wide SIMD Registers and Vector Processing Unit (VPU): VPU has been treated as the most important feature of Xeon Phi by previous studies [19,33,24,8]. The reason is that the Intel Xeon Phi coprocessor has doubled the SIMD lane width compared to Intel Xeon processor, i.e., 256-bit to 512bit, which means that it can process 16 (8) identical floating point (double precision) operations at the same time.…”

Section: Intel Xeon Phi Architecturementioning

confidence: 99%

“…Wide SIMD Registers and Vector Processing Unit (VPU): VPU has been treated as the most important feature of Xeon Phi by previous studies [19,33,24,8]. The reason is that the Intel Xeon Phi coprocessor has doubled the SIMD lane width compared to Intel Xeon processor, i.e., 256-bit to 512bit, which means that it can process 16 (8) identical floating point (double precision) operations at the same time. More Flexible SIMD Programming with Gather/Scatter: Unlike earlier SSE instructions supported by Intel CPUs, we have a new 512-bit SIMD instruction set called the Intel Initial Many Core Instructions (Intel IMCI).…”

Section: Intel Xeon Phi Architecturementioning

confidence: 99%

Exploiting recent SIMD architectural advances for irregular applications

Chen

Jiang

Agrawal

2016

Proceedings of the 2016 International Symposium on Code Generation and Optimization

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A broad class of applications involve indirect or datadependent memory accesses and are referred to as irregular applications. Recent developments in SIMD architectures-specifically, the emergence of wider SIMD lanes, combination of SIMD parallelism with many-core MIMD parallelism, and more flexible programming APIs-are providing new opportunities as well as challenges for this class of applications. In this paper, we propose a general optimization methodology, to effectively optimize different subclasses of irregular applications. Based on the observation that all applications with indirect memory accesses can be viewed as sparse matrix computations, we design an optimization methodology, which includes three sub-steps: 1) locality enhancement through tiling, 2) data access pattern identification, and 3) write conflict removal at both SIMD and MIMD levels. This method has been applied to unstructured grids, molecular dynamics, and graph applications, in addition to sparse matrix computations. The speedups achieved by our single threaded vectorized code over serial code is up to 9.05, whereas the overall speedup while utilizing both SIMD and MIMD (61 cores in Intel Xeon Phi) with our approach is up to 467.1. Further optimization using matrix reordering on irregular reductions and graph algorithms is able to achieve an incremental speedup of up to 1.69, though at a relatively high preprocessing cost. Moreover, SpMM using our approach outperforms routines from a highly optimized commercial library by up to 2.81x.

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HyPHI - Task Based Hybrid Execution C++ Library for the Intel Xeon Phi Coprocessor

Cited by 11 publications

References 6 publications

Automatic Tuning of a Parallel Pattern Library for Heterogeneous Systems with Intel Xeon Phi

Automatic Tuning of a Parallel Pattern Library for Heterogeneous Systems with Intel Xeon Phi

Towards High-Level Parallel Patterns in OpenCL

Exploiting recent SIMD architectural advances for irregular applications

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