Hydrogen Annealed Silicon Wafer

Nadahara, Soichi; Kubota, Hirofumi; Samata, Shuichi

doi:10.4028/www.scientific.net/ssp.57-58.19

Cited by 9 publications

(3 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The results are shown in figures 3(a) and (b), respectively. It is well known that hydrogen suppresses defect aggregations in Si [60][61][62]. Defects that are prevented from aggregating tend to diffuse out to the NW surface and eventually disappear.…”

Section: Resultsmentioning

confidence: 99%

Defect control and Si/Ge core–shell heterojunction formation on silicon nanowire surfaces formed using the top-down method

Fukata¹,

Jevasuwan²,

Sun³

et al. 2022

Nanotechnology

View full text Add to dashboard Cite

Control of surface defects and impurity doping are important keys to realizing devices that use semiconductor nanowires (NWs). As a structure capable of suppressing impurity scattering, p-Si/i (intrinsic)-Ge core-shell NWs with radial heterojunctions inside the NWs were formed. When forming NWs using a top-down method, the positions of the NWs can be controlled, but their surface is damaged. When heat treatment for repairing surface damage is performed, the surface roughness of the NWs closely depends on the kind of atmospheric gas. Oxidation and chemical etching prior to shell formation removes the surface damaged layer on p-SiNWs and simultaneously achieves a reduction in the diameter of the NWs. Finally, hole gas accumulation, which is important for suppressing impurity scattering, can be observed in the i-Ge layers of p-Si/i-Ge core-shell NWs.

show abstract

Section: Resultsmentioning

confidence: 99%

Defect control and Si/Ge core–shell heterojunction formation on silicon nanowire surfaces formed using the top-down method

Fukata¹,

Jevasuwan²,

Sun³

et al. 2022

Nanotechnology

View full text Add to dashboard Cite

show abstract

“…It was found that high temperature annealing can help control and manage also other types of crystal defects, not simply oxide precipitates. The COP defects on the wafer surface can be annihilated during high temperature annealing in hydrogen (Nadahara et al, 1997), or in argon ambient (Adachi et al, 1998). As shown in Fig.…”

Section: Wafer Annealingmentioning

confidence: 99%

Defect Engineering During Czochralski Crystal Growth and Silicon Wafer Manufacturing

Válek¹,

Šik²

2012

Modern Aspects of Bulk Crystal and Thin Film Preparation

View full text Add to dashboard Cite

Modern Aspects of Bulk Crystal and Thin Film Preparation 44 2.1 Czochralski growth of silicon crystals Today´s Czochralski (CZ) grown silicon single crystals are produced in a mass scale in diameters of up to 300 mm, but the 150 mm and 200 mm processes are still considered as standard. A typical CZ puller is shown in Fig. 1. The puller consists of an upper and lower chamber formed by steel water-cooled shells. The lower chamber contains a graphite hot zone with active central part and thermally insulating outer parts. A silica crucible is placed in the heart of the hot zone which is supported by a graphite susceptor on the pedestal attached to the lower shaft. The seed holder is fastened onto the upper shaft (or affixed to a cable). The heater is a meandering-coil element heated by high electric current. Both chambers are piped to a vacuum system. The puller is typically purged with inert gas (usually argon). In the beginning of the process the quartz crucible is loaded with a charge of polysilicon chunks and the single crystalline seed is fitted into the seed holder. After closing the puller the chambers are evacuated and refilled by inert gas to the desired process pressure. The process starts with melting the polysilicon charge by applying high power to the heater. Once the charge is molten, the melt flow is stabilized under steady conditions and the seed is lowered towards the melt. After the seed is dipped into the melt, the system is adjusted to achieve a stable interface between the melt and the seed crystal. Pulling the seed upwards crystallizes the melt at the solid-liquid interface and the crystal proceeds to grow.

show abstract

“…The external origins of dielectric breakdown, such as crystal-originated particles (COPs) 1) and bulk micro defects, have been reduced by improvements of crystal growth technologies and thermal treatments of Si wafers. [2][3][4] With the improvements, we are now approaching the real understanding of the reliability of dielectric films. However, we often ignore the nonuniformity of the films, and interpret the experimental outputs as the results from its intrinsic characteristics.…”

Section: Introductionmentioning

confidence: 99%

Reliability factors of ultrathin dielectric films based on highly controlled SiO₂films

Hasunuma¹,

Kawamura²,

Yamabe³

2018

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

Two main factors determine the reliability of ultrathin SiO 2 films thermally grown on Si when subjected to long-term electrical stress. One of them is two-dimensional thickness uniformity for suppressing the decrease in Weibull slope. The other is film density distribution, which affects the degradation rate during application of high electric stress. The importance of thermal process optimization in inhibiting density fluctuation is demonstrated.

show abstract

Hydrogen Annealed Silicon Wafer

Cited by 9 publications

References 0 publications

Defect control and Si/Ge core–shell heterojunction formation on silicon nanowire surfaces formed using the top-down method

Defect control and Si/Ge core–shell heterojunction formation on silicon nanowire surfaces formed using the top-down method

Defect Engineering During Czochralski Crystal Growth and Silicon Wafer Manufacturing

Reliability factors of ultrathin dielectric films based on highly controlled SiO₂films

Contact Info

Product

Resources

About

Hydrogen Annealed Silicon Wafer

Cited by 9 publications

References 0 publications

Defect control and Si/Ge core–shell heterojunction formation on silicon nanowire surfaces formed using the top-down method

Defect control and Si/Ge core–shell heterojunction formation on silicon nanowire surfaces formed using the top-down method

Defect Engineering During Czochralski Crystal Growth and Silicon Wafer Manufacturing

Reliability factors of ultrathin dielectric films based on highly controlled SiO2films

Contact Info

Product

Resources

About

Reliability factors of ultrathin dielectric films based on highly controlled SiO₂films