Hybrid Simulation for Energy Estimation of Embedded Software

Muttreja, A.; Raghunathan, Anand; Ravi, S.; Jha, Niraj K.

doi:10.1109/tcad.2007.895760

Cited by 14 publications

(6 citation statements)

References 20 publications

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“…Finally, Muttreja et.al. [5] proposed a hybrid single-core simulation technique for SW energy estimation, but the proposed implementation is intrusive, assuming some source code modifications for support of simulation mode switching.…”

Section: Related Workmentioning

confidence: 99%

Hybrid simulation for extensible processor cores

Jovic¹,

Yakoushkin²,

Murillo³

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Due to their good flexibility-performance trade-off, Application Specific Instruction-set Processors (ASIPs) have been identified as a valuable component in modern embedded systems, especially the extensible ones, achieving good cost-efficiency trade-offs. Since the generation of the described hardware is usually automated to a high extent, in order to deliver an ASIP-based design in due time, developers are limited by the performance of the underlying simulation techniques for software development. On the other hand, the Hybrid Processor simulation technology (HySim), which enables dynamic run-time switching between native and instruction-accurate simulation, has reported high speed-up values for some fixed architectures. This paper presents enhanced HySim technology for extensible cores, based on a layered simulation infrastructure. This technology has shown a speed-up on a per-function basis of two orders of magnitude for a realistic MIMO OFDM benchmark on a multi-core platform with customized Xtensa cores by Tensilica.

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Section: Related Workmentioning

confidence: 99%

Hybrid simulation for extensible processor cores

Jovic¹,

Yakoushkin²,

Murillo³

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

show abstract

“…In this paper, the proposed framework exploits the latter idea, which is quite the same as [8] [9]. Although sharing the idea with these previous works, the program partition is quite different from them in the granularity and technique.…”

Section: Related Workmentioning

confidence: 99%

An ultra-fast hybrid simulation framework for ASIP

Qiu

Gao

Jiang

et al. 2011

2011 18th IEEE International Conference on Electronics, Circuits, and Systems

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ISS (Instruction Set Simulator) plays an important role in pre-silicon software development for ASIP. However, the speed of traditional simulation is too slow to effectively support full-scale software development. In this paper, we propose a hybrid simulation framework which further improves the previous simulation methods by aggressively utilizing the host machine resources. The utilization is achieved by categorizing instructions of ASIP application into two types, namely custom and basic instructions, via binary instrumentation. Then in a way of hybrid simulation, only custom instructions are simulated on the ISS and basic instructions are executed fast and natively on the host machine. We implement this framework for an industrial ASIP to validate our approach. Experimental results show that when the implemented ISS, namely GS-Sim, is applied to practical multimedia decoders, an average simulation speed up to 1058.5MIPS can be achieved, which is 34.7 times of the stateof-art dynamic binary translation simulator and is the fastest to the best of our knowledge.

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“…Finally, only a very few benchmarks have been evaluated. A similar hybrid approach targeting software energy estimation has been proposed earlier in [19,20].…”

Section: Performance Modelling In Fast Instruction Set Simulatorsmentioning

confidence: 99%

Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator

Böhm

Franke

Topham

2010

2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation

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Abstract. Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-time (JIT) dynamic binary translation (DBT) techniques are able to simulate complex embedded processors at speeds above 500 MIPS. However, these functional ISS do not provide microarchitectural observability. In contrast, low-level cycle-accurate ISS are too slow to simulate full-scale applications, forcing developers to revert to FPGA-based simulations. In this paper we demonstrate that it is possible to run ultra-high speed cycle-accurate instruction set simulations surpassing FPGA-based simulation speeds. We extend the JIT DBT engine of our ISS and augment JIT generated code with a verified cycle-accurate processor model. Our approach can model any microarchitectural configuration, does not rely on prior profiling, instrumentation, or compilation, and works for all binaries targeting a state-of-the-art embedded processor implementing the ARCompact TM instruction set architecture (ISA). We achieve simulation speeds up to 88 MIPS on a standard x86 desktop computer for the industry standard EEMBC, COREMARK and BIOPERF benchmark suites.

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Hybrid Simulation for Energy Estimation of Embedded Software

Cited by 14 publications

References 20 publications

Hybrid simulation for extensible processor cores

Hybrid simulation for extensible processor cores

An ultra-fast hybrid simulation framework for ASIP

Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator

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