Hybrid scheduling to enhance reliability of real-time tasks running on reconfigurable devices

Custom Soft-Core RISC Processor Validation Based on Real-Time Event Handling Scheduler FPGA Implementation

“…Reconfigurable devices used in real-time embedded systems and research on hybrid fault-tolerant scheduling are a real challenge to improve the reliability of real-time independent periodic hardware tasks. The technique proposed in [9] schedules tasks according to the EDF-NP policy, and candidate spare tasks are selected to load free processing periods. In the next phase, an event-triggered dispatcher decides which candidate spare tasks should be configured and executed on the FPGA at runtime.…”

“…In the next phase, an event-triggered dispatcher decides which candidate spare tasks should be configured and executed on the FPGA at runtime. Experimental results show that the hybrid scheduling technique proposed in [9] improves the mean time to system failure by an average factor of 1.22 compared to other scheduling algorithms. In mixed-criticality systems, software fault-tolerance techniques are available to mitigate hardware failures, but adapting them to real-time systems is challenging due to the overhead introduced.…”

“…The proposed vector processor can be scaled to meet the performance requirements of massively parallel computational tasks, but its timing behavior can remain simple enough to be efficiently analyzable. The same idea from existing studies is the improvement or proposal of new scheduling algorithms [9], [14], [15], [17], [18], [20] and their implementation in hardware or in hybrid form for processor acceleration. Another similar idea introduced in articles [10], [11], [12], [16], HW_nMPRA_RTOS, is to integrate operating system functions, schedulers or external accelerators in hardware, which are then integrated into real-time or even mixed-criticality systems.…”

Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets

“…The values of 𝜌 𝑘 can be easily estimated for different devices using existing tools [10]. Therefore, following the general reliability formulation, the probability of an 𝑘-bit event occurring m times during the task execution (and, therefore, affecting totally 𝑚 • 𝑘 bits) is 1 :…”

“…Static random-access memory (SRAM)-based Field Programmable Gate Arrays (FPGAs) feature low-cost and offer an interesting trade-off between performance and flexibility. Such FPGAs can be reconfigured at runtime to execute different functionalities in a time-multiplexed manner [1]. Therefore, they have found many applications in space computing systems [2], where space qualified software and devices are typically used to guarantee data integrity and a correct functionality [3].…”