A prefetch-aware scheduling for FPGA-based multi-task graph systems

Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets

“…where 𝐶𝑇 𝜏 is task computation time, 𝐶𝐶 𝜏 is the number of basic reconfigurable elements, and 𝑇𝑆 𝜏 is task size in the configuration memory (number of configuration bits). The computation time of tasks is expressed in terms of milliseconds, which is consistent with typical delays of tasks running on SRAM-based FPGAs [20]. Task size 𝑇𝑆 𝜏 depends on 𝐶𝐶 𝜏 and some features of the underlying FPGA that will be discussed in the next subsection.…”

A Survey: FPGA‐Based Dynamic Scheduling of Hardware Tasks

“…However, the above scheduling algorithms are only suitable for single application processing. Aiming at the FPGA hardware task scheduling problem in continuous multiple application scenarios, Ramezani [ 19 ] proposed a Forefront‐fetch technology. During an application's execution, some tasks of the following application to be processed are packaged and configured in advance.…”

“…From the perspective of ensuring the universality of FPGA accelerators, Jiang et al [75] and Ma et al [76] designed scheduling strategies that can apply to neural networks of different types and different precision. Banerjee [15] √ − − × Marconi [45] − × √ − Resano [16] √ − − × Tabero [46] − √ √ − Khuat [18] √ − √ × Marconi [47] − √ √ − Ramezani [19] √ − − × Xu [48] − √ √ − Bauer [20] √ − − × Enemali [49] √ − √ − Dai [21] √ − √ × Diessel [51] × − √ × Cattaneo [22] √ − √ × Gericota [52] × − √ × AlWattar [25] √ − − × George [53] × × √ × Hariharan [26] √ − − × MoralesVillanueva [54] × × √ × Mansub [27] √ − √ √ Enemali [55] − − √ − Deiana [28] √ − − × Yuh [57] √ − − √ Fekete [29] − √ − − Li [58] √ − − √ Marconi [30] − √ − − Hsieh [59] √ − − √ Cadi [31] √ √ − − Pham [60] √ − − √ Abdallah [32] √ √ − − Wang [61] √ − − √ Ahmadinia [33] − √ − − Pham [62] √ − − √ Sheng [34] − √ − − Zhou [63] √ − − √ Huang [35] − √ √ × Ghorbani [64] − − − √ Yoosefi [36] − √ − − Khodabandeloo [65] √ − − √ Bazargan [37] − − √ − Yang…”

Resource Partitioning and Application Scheduling with Module Merging on Dynamically and Partially Reconfigurable FPGAs

“…Refs. [11][12][13] take the technique of perfecting for accomplishing this objective. Some researchers use module reuse to optimize reconfiguration time and power consumption in [14,15].…”

“…In order to more clearly show the relative sizes of SL solved by different methods, Performance Improvement Ratio (PIR) was introduced to represent the relative difference of SL as follows: PIR = SL SA − SL other SL other (11) When PIR = 0, SA-based algorithm had the same scheduling length as other algorithm; When PIR < 0, the scheduling length solved by SA-based algorithm was better than other algorithm, |PIR| means that the difference between SA-based algorithm and other algorithm accounted for the proportion of other algorithm;…”