Hybrid‐mode single‐slope ADC with improved linearity and reduced conversion time for CMOS image sensors

Abstract

In the paper, a single-slope analog-to-digital converter (ADC) for integrated CMOS image sensor applications with an improved technique of conversion has been proposed. The proposed hybrid-mode ADC automatically uses one of the following conversion techniques: time based (i.e. PWM) or voltage based (i.e. single-slope). During the ADC operation, the clock frequency and reference voltage are modified in order to reduce the conversion time and achieve the optimal linearity. Owing to this, the pixel using a photodiode working in the integration mode achieves a linear photoconversion characteristics (irradiance to digital number), and the conversion period, which is determined by the darkest parts of a scene, is reduced by an order of magnitude comparing with known ADC solutions. The proposed conversion technique has been validated with the ASIC prototype of a CMOS imager containing photosensors integrated with the ADCs. The ASIC was fabricated in standard 0.18 μm CMOS technology. A specialized measurement system has been used to optimize linearity in the hybrid-mode conversion (integral nonlinearity below 2 LSB). The conversion period has been reduced 15 times compared with the standard technique. Measurements confirm functionality of the proposed approach, implemented within a small pixel area.

Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors

“…This is due to pixel ADCs going into voltage mode, which is not included in the presented linearity optimization algorithm. The final 21st iteration was performed after optimization of the waveform of V ramp voltage, the principles of which are presented in Reference [ 18 ]. Figure 14 shows the improvement of the INL waveform for the low illumination level after the V ramp optimization (red plot) based on a semi-stochastic algorithm [ 22 ].…”

“…Figure 2 shows the principle of the hybrid conversion in the CMOS imager presented in Reference [ 18 ]. The conversion starts at the end of the reset pulse (zero on the time axis) and finishes at T f .…”

“…When the V s node discharges to the V ref within the time T i , then the time mode is used. For the conversion in the time mode (clocking phase 1a) to be linear, the intervals between successive clock pulses are increased [ 18 , 19 ]. It can be easily derived from (1) that without such clock period correction the imager’s digital result of the conversion would be inversely proportional to the photocurrent.…”

“…To maintain good linearity during the entire conversion, the time and voltage modes must be “glued” together in such a way that the following formula is satisfied: N v = N t-half , where N v is the number of clock pulses in the voltage mode and N t-half is the number of clock pulses in the second half of the time mode interval (T i /2 to T i ). Proof and more details can be found in Reference [ 18 ]. Condition (2) must be satisfied to allow a gain correction based on multiplying the response of an individual pixel by a specific coefficient (flat-field correction).…”

“…In Reference [ 17 ], noise reduction and dynamic range improvement were achieved by using multiple ramps in the reference voltage. In Reference [ 18 ], the hybrid (time and voltage mode) technique of analog-to-digital conversion was introduced, which allows to shorten the conversion time and at the same time maintains the linear light-to-digital characteristic. In the presented paper, an improved technique of the hybrid analog-to-digital conversion with a further reduction of the linearity error and correction of the pixel level gain and offset is proposed.…”