Hybrid DPWM implementation using coarse and fine programmable ADLL

Hybrid Linearized Class-BD Double Sided (LBDD) Digital Pulse Width Modulator (DPWM) for Class-BD Audio Amplifiers

“…The essential limitation of the digital-to-time converter (DTC), which converts obtained from the noise shaping process N rq -bit positions of the leading and trailing edges of the PWM pulse within each n-th switching period into a physical sequence of 1-bit modulated PWM pulses is excessive clock speed. The DTC with N rq -bit resolution, based on counter method in downcounting mode, requires clock frequency [15][16][17]: ( 7 ) giving time resolution of generated pulse: Consequently to assure N rq -bit resolution, DTC processing error must be smaller than ( ) delay cells, additional and variable delay introduced by each path connecting delay line tap with appropriate multiplexer's input as well some other factors like Process, Voltage and Temperature (PVT) variations and different mismatches result in nonlinearity of the quantizer. However linear characteristic with evenly distributed steps can be achieved for low resolution of the converter, when delay line is formed of small number of the delay cells, closed in feedback loop of the DLL [12][13][14][15][16].…”

“…Practically, even for a requantized resolution N rq -bit of the digital output, a required clock frequency CLK f is too high to implement the DCT, therefore to circumvent the high-frequency clock problem a hybrid DCT is used [11][12][13][14][15][16][17], which integrates the counter method and a method based on the tapped delay line.…”

Hybrid LBDD PWM modulator for digital class-BD audio amplifier based on STM32F407VGT6 microcontroller and analog DLL

“…LBDD modulator is more sophisticated than other LPWM, and also more challenging because of real-time computational cost of the processor, as it is composed of two linearized Class-AD double sided (LADD) modulators converting within each switching period c nT the calculated data of the leading-and trailing edge locations ( ) (n t k and ) (n t p , respectively) of the PWM pulses, into the two physical trains of the PWM pulses to control the power transistors of the Class-BD amplifier [7][8].…”

“…The linear quantizer based on the TVCDL put into ADLL, processing the data of LSB (2:0) part, circumvents the highclock frequency problem, however, the practical realization may be cumbersome because of asymmetrical layout of the delay cells, additional and variable delay introduced by each path connecting delay line tap with appropriate multiplexer's input as well some other factors like PVT variations and different mismatches result in nonlinearity of the quantizer [7][8][9][10][11]. An unacceptable quantizer errors may be caused also by delays contributed by signal paths connecting the subsystem converting MSBs with that one, converting LSBs, and also by delays contributed by the building blocks of the subsystem converting LSBs.…”

“…Interpolation of the PCM audio data stream sampled at the frequency s f provides a target data stream at the switching Even for moderate resolution (exceeding 8 bits), simple counter method requires practically too high clock frequencyThe quantizer processing the data of LSB (2:0) comprises TVCDL implemented as a cascade of m 2 identical variabledelay segments closed in negative feedback loop of the ADLL, at the same time the delay introduced by single segment equals[7][8][9][10][11][12][13]:…”