2015 22nd International Conference Mixed Design of Integrated Circuits &Amp; Systems (MIXDES) 2015
DOI: 10.1109/mixdes.2015.7208585
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Hybrid LBDD PWM modulator for digital class-BD audio amplifier based on STM32F407VGT6 microcontroller and analog DLL

Abstract: In the paper a new architecture and implementation of the 9-bit hybrid LBDD PWM modulator for digital Class-BD audio amplifier has been proposed. First, the PCM audio signal is transformed into the requantized to 9-bit resolution DPWM data, using LBDD algorithm. Then the 9-bit DPWM data are converted into the two physical trains of PWM pulses to control the output power transistors, using two hybrid digital to time converters (HDTC). The HDTC converts 6 MSB data on the base counter method using advanced-contro… Show more

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Cited by 3 publications
(6 citation statements)
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“…Jasielski investigated the LBDD PWM hybrid modulator for BD-class digital audio amplifier based on the STM32F407VGT6 microcontroller and analog DLL. A new architecture and implementation of the 9-bit hybrid LBDD PWM modulator for Class-BD digital audio amplifiers had been proposed [17]. Ravi Kumar studied a microprocessorbased closed-loop speed control on DC motors using PWM.…”
Section: Khan Designed and Manufactured Digital Mosfet-basedmentioning
confidence: 99%
“…Jasielski investigated the LBDD PWM hybrid modulator for BD-class digital audio amplifier based on the STM32F407VGT6 microcontroller and analog DLL. A new architecture and implementation of the 9-bit hybrid LBDD PWM modulator for Class-BD digital audio amplifiers had been proposed [17]. Ravi Kumar studied a microprocessorbased closed-loop speed control on DC motors using PWM.…”
Section: Khan Designed and Manufactured Digital Mosfet-basedmentioning
confidence: 99%
“…The essential limitation of the digital-to-time converter (DTC), which converts obtained from the noise shaping process N rq -bit positions of the leading and trailing edges of the PWM pulse within each n-th switching period into a physical sequence of 1-bit modulated PWM pulses is excessive clock speed. The DTC with N rq -bit resolution, based on counter method in downcounting mode, requires clock frequency [15][16][17]: ( 7 ) giving time resolution of generated pulse: Consequently to assure N rq -bit resolution, DTC processing error must be smaller than ( ) delay cells, additional and variable delay introduced by each path connecting delay line tap with appropriate multiplexer's input as well some other factors like Process, Voltage and Temperature (PVT) variations and different mismatches result in nonlinearity of the quantizer. However linear characteristic with evenly distributed steps can be achieved for low resolution of the converter, when delay line is formed of small number of the delay cells, closed in feedback loop of the DLL [12][13][14][15][16].…”
Section: System Clock Selection and Architecture Of The Proposed 9-bimentioning
confidence: 99%
“…Integration of both afore-described methods into a hybrid DTC allows a trade-off between the high-frequency clock requirement and quantization linearity of the digital to time conversion [13][14][15][16].…”
Section: System Clock Selection and Architecture Of The Proposed 9-bimentioning
confidence: 99%
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