Hybrid Circuit of Memristor and Complementary Metal-Oxide-Semiconductor for Defect-Tolerant Spatial Pooling with Boost-Factor Adjustment

Abstract

Hierarchical Temporal Memory (HTM) has been known as a software framework to model the brain’s neocortical operation. However, mimicking the brain’s neocortical operation by not software but hardware is more desirable, because the hardware can not only describe the neocortical operation, but can also employ the brain’s architectural advantages. To develop a hybrid circuit of memristor and Complementary Metal-Oxide-Semiconductor (CMOS) for realizing HTM’s spatial pooler (SP) by hardware, memristor defects such as stuck-at-faults and variations should be considered. For solving the defect problem, we first show that the boost-factor adjustment can make HTM’s SP defect-tolerant, because the false activation of defective columns are suppressed. Second, we propose a memristor-CMOS hybrid circuit with the boost-factor adjustment to realize this defect-tolerant SP by hardware. The proposed circuit does not rely on the conventional defect-aware mapping scheme, which cannot avoid the false activation of defective columns. For the Modified subset of National Institute of Standards and Technology (MNIST) vectors, the boost-factor adjusted crossbar with defects = 10% shows a rate loss of only ~0.6%, compared to the ideal crossbar with defects = 0%. On the contrary, the defect-aware mapping without the boost-factor adjustment demonstrates a significant rate loss of ~21.0%. The energy overhead of the boost-factor adjustment is only ~0.05% of the programming energy of memristor synapse crossbar.

Exploiting defective RRAM array as synapses of HTM spatial pooler with boost-factor adjustment scheme for defect-tolerant neuromorphic systems

“…However, the fault-aware defect mapping scheme needs to use the complex digital circuits occupying a large layout area 28 . We thus developed the boost-factor adjustment scheme, where the erroneous neurons connected with many defective synapses can be suppressed in a self-controlled manner without using the defect map measured during the previous diagnostic process 25 . The boost-factor adjustment scheme suppressed the gain of the current-to-voltage converter, when the column was activated frequently due to many failures.…”

“…While most studies have focused on achieving the multilevel states [13][14][15][16][17][18][19] , reliability issues of the multiple states that play a crucial role in the VMM from operational perspective have been rarely explored 22,23 . More importantly, a device failure in the crossbar RRAM array causes significant performance degradation in the neuromorphic systems 24,25 . Among the various neuromorphic architectures, the crossbar array can be served as a spatial pooler (SP) for hierarchical temporal memory (HTM) that describes the functionality of the human neocortex 26 , as shown in Fig.…”

“…However, the drawback is that complicated circuits and capacitors required to read and verify all RRAMs occupy a large area. To minimize the effect of the failed RRAMs without using the fault-aware mapping, we introduced a boost-adjustment technique implemented with simple circuits proposed in the previous work 25 . However, the types of the failures that can be specifically observed in real devices dedicated to the synaptic element have not been discussed.…”

“…The simplified schematic diagram of the hybrid circuit was shown in the box, and detailed operation was described in the reference25 . Here a column with a large number of defective RRAMs was less activated by the boost-factor adjustment25 .Vol:. (1234567890) Scientific RepoRtS | (2020) 10:11703 | https://doi.org/10.1038/s41598-020-68547-5…”

Memristors for Neuromorphic Circuits and Artificial Intelligence Applications

“…Application of the circuit to the Enhanced-MNIST database demonstrates very good accuracy in both word and sentence recognition. In their second paper, they deal with reducing the effects of defects in the memristor crossbars such a stuck-at faults and memristor variations [22]. First, they show that the boost-factor adjustment can make the system fault-tolerant by suppressing the activation of defective columns.…”