Hybrid AlGaN/GaN high‐electron mobility transistor: design and simulation

Abstract

In this study, the authors propose a novel structure of high-electron mobility transistor (HEMT) with significantly improved performance. The novelty of the proposed HEMT is the realisation of two parallel induced electron layers under the source and drain electrode, one in the form of two-dimensional (2D) electron gas (2DEG) and the other in the form of charge plasma electron gas (CPEG). The proposed device is a hetrostructure GaN/AlGaN device, therefore, a 2DEG gets created. However, two metal electrodes at the source and drain terminals are used in the proposed device, which induce CPEG in an undoped AlGaN film under the source and drain electrode. Therefore, the proposed HEMT device is hybrid and has a combination of CPEG and the 2DEG. A two-dimensional (2D) calibrated simulation study of the proposed device has revealed that its hybrid nature has improved its performance significantly in comparison to the conventional HEMT device having 2DEG only. It has been observed that the ON current has enhanced by 115%, transconductance (g m) by 168%, cutoff frequency (f T) by 71% and maximum oscillation frequency (f max) by 65% in comparison to the conventional HEMT.

Characterization of AlGaN/GaN based HEMT for low noise and high frequency application

“…We reproduced the results of a fabricated device by Ye et al 29 During calibration, the device structure, its dimensions, and all other parameters have been kept the same as used in Ye et al 29 We reproduced I D À V DS curve at V GS = 1 V, V GS = 0 V and V GS = À1 V and I D À V GS curve at V DS = 10 V as shown in Figures 2(A),(B), respectively, for calibration. Our approach of calibration is in line with the approach adopted by the authors in Verma et al [30][31][32] Figure 3(A)-(M) illustrates the steps required for the fabrication of the proposed AlGaN/GaN based HEMT. Metal organic chemical vapor deposition (MOCVD) process is used to grow an undoped AlN nucleation layer (see Figure 3 (A)).…”

“…We reproduced the results of a fabricated device by Ye et al 29 During calibration, the device structure, its dimensions, and all other parameters have been kept the same as used in Ye et al 29 We reproduced I D − V DS curve at V GS = 1 V, V GS = 0 V and V GS = −1 V and I D − V GS curve at V DS = 10 V as shown in Figures 2(A),(B), respectively, for calibration. Our approach of calibration is in line with the approach adopted by the authors in Verma et al 30–32 …”

Al0.30Ga0.70N /GaN MODFET with triple-teeth metal for RF and high-power applications

“…We also reproduced the input characteristics, which have been depicted in figure 2(b) for the purpose of calibration. We have followed the calibration method adopted by authors in [24][25][26].…”

Performance Assessments of Gate Engineered Dopingless Schottky Tunnel MOSFET in presence of Interfacial Trap Charges

“…Continuous downscaling in device dimensions of conventional MOSFET causes several short channel effects(SCE), higher leakage currents, reliability issues, and self-heating effects. In addition, the necessity of abrupt doping and shallow junctions limits the device performances [5][6][7][8][9]. The ultrathin fully depleted SOI MOSFETs can give better solutions to the above problems [8].…”