HW/SW Co-design of an IEEE 802.11a/g Receiver on Xilinx Zynq SoC using High-Level Synthesis

Nouri, Sajjad; Rettkowski, Jens; Göhringer, Diana; Nurmi, Jari

doi:10.1145/3120895.3120908

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2018

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“…The increasing demand for custom hardware has driven embedded software developers towards more complex architectures, employing heterogeneous systems which combine together processing units and hardware accelerators [5]- [7]. By doing so, computationally-intensive operations can be unloaded from the CPU to the dedicated circuit.…”

Section: Introductionmentioning

confidence: 99%

Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesis

Cacciotti

Camus

Schlachter

et al. 2018

2018 31st IEEE International System-on-Chip Conference (SOCC)

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In this paper, the hardware acceleration of a tonemapping algorithm for High-Dynamic-Range image processing is presented. Starting from the C++ source code, High-Level Synthesis has been performed using Xilinx SDSoC for a Xilinx Zynq SoC device. After an initial code optimization to improve the memory access bottleneck, SDSoC pragmas have been introduced to boost system performance through an increased parallelism. Preliminary results have shown significant reductions in the execution time and the energy consumption compared to the conventional software implementation.

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Section: Introductionmentioning

confidence: 99%