HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC

Valente, Luca; Tortorella, Yvan; Sinigaglia, Mattia; Tagliavini, Giuseppe; Capotondi, Alessandro; Benini, Luca; Rossi, Davide

doi:10.23919/date56975.2023.10137252

Cited by 6 publications

(1 citation statement)

References 11 publications

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“…At 0.625V, delivering 1.1Gbps, the power consumption is 0.8mW, with 75% of the IOs. More details about the HyperRAM controller's performance and power characterization, as well as comparisons with traditional DDR controllers, can be found in [53].…”

Section: Implementation and Measurementsmentioning

confidence: 99%

Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs

Valente,

Veeran,

Sinigaglia

et al. 2023

2023 IEEE Hot Chips 35 Symposium (HCS)

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The rapid advancement of energy-efficient parallel ultra-low-power (ULP) µcontrollers units (MCUs) is enabling the development of autonomous nano-sized unmanned aerial vehicles (nano-UAVs). These sub-10cm drones represent the next generation of unobtrusive robotic helpers and ubiquitous smart sensors. However, nano-UAVs face significant power and payload constraints while requiring advanced computing capabilities akin to standard drones, including real-time Machine Learning (ML) performance and the safe co-existence of general-purpose and real-time OSs. Although some advanced parallel ULP MCUs offer the necessary ML computing capabilities within the prescribed power limits, they rely on small main memories (<1MB) and µcontroller-class CPUs with no virtualization or security features, and hence only support simple bare-metal runtimes. In this work, we present Shaheen, a 9mm 2 200mW SoC implemented in 22nm FDX technology. Differently from state-of-the-art MCUs, Shaheen integrates a Linux-capable RV64 core, compliant with the v1.0 ratified Hypervisor extension and equipped with timing channel protection, along with a low-cost and low-power memory controller exposing up to 512MB of off-chip low-cost low-power HyperRAM directly to the CPU. At the same time, it integrates a fully programmable energy-and area-efficient multi-core cluster of RV32 cores optimized for general-purpose DSP as well as reduced-and mixed-precision ML. To the best of the authors' knowledge, it is the first silicon prototype of a ULP SoC coupling the RV64 and RV32 cores in a heterogeneous host+accelerator architecture fully based on the RISC-V ISA. We demonstrate the capabilities of the proposed SoC on a wide range of benchmarks relevant to nano-UAV applications including general-purpose DSP as well as inference and online learning of quantized DNNs. The cluster can deliver up to 90GOp/s and up to 1.8TOp/s/W on 2-bit integer kernels and up to 7.9GFLOp/s and up to 150GFLOp/s/W on 16-bit FP kernels.

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Section: Implementation and Measurementsmentioning

confidence: 99%

Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs

Valente,

Veeran,

Sinigaglia

et al. 2023

2023 IEEE Hot Chips 35 Symposium (HCS)

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Sustainable Computing Through Open Standard ISAs: Leveraging Tailor-Fit Hardware Designs for Circular Economies

Mariscal-Melgar,

Moritz,

Redlich

et al. 2023

Lecture Notes in Production Engineering

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“Interrupting” the Status Quo: A First Glance at the RISC-V Advanced Interrupt Architecture (AIA)

Marques,

Rodríguez,

Sá

et al. 2024

IEEE Access

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Interrupt controllers are a crucial component in computing platforms. From cloud computing to embedded systems, interrupts and respective controllers enable more efficient management and operation of a platform's resources. Modern computer architectures incorporate hardware interrupt controllers (e.g., Arm Generic Interrupt Controller (GIC)) that are well-established in modern processors and system-onchips (SoCs). This article describes our work and research on developing the first open-source RISC-V Advanced Interrupt Architecture (AIA) IP compliant with the recently ratified specification (v1.0). Our contribution is multifold and encompasses architecture, microarchitecture, and evaluation. In particular, we explored alternative designs and microarchitectural enhancements for the implemented IP to cope with mixed-criticality systems (MCS) requirements (e.g., real-time and predictability). From this exploration, we highlight the proposed Integrated Embedded AIA (IE-AIA) design. For each configuration, we assess the impact on hardware utilization and interrupt latency. Due to the increased proliferation of virtualization in MCS, we measured the interrupt latency for a system configuration built atop the Bao hypervisor. At the macro level (i.e., considering both hardware and software), and in particular for a full-blown virtualization stack, we observed a reduction of ∼99.5% in the average interrupt latency when comparing the Platform-Level Interrupt Controller (PLIC) IP (full trap and emulation) with the standard AIA IP (no hypervisor mediation due to IMSIC direct interrupt injection). For the IE-AIA, our evaluation focused on the micro view (i.e., hardware only), where we observed that under interference, the IE-AIA IP shows a reduction of ∼ 7× in the average interrupt latency and deterministic behavior compared to the standard AIA implementation. We also provide the first empirical-based comparison between the RISC-V PLIC and the RISC-V AIA. Finally, all artifacts described in this article are open source to foster collaboration and further explore additional design configurations.

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HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC

Cited by 6 publications

References 11 publications

Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs

Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs

Sustainable Computing Through Open Standard ISAs: Leveraging Tailor-Fit Hardware Designs for Circular Economies

“Interrupting” the Status Quo: A First Glance at the RISC-V Advanced Interrupt Architecture (AIA)

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