Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs

Abstract

The rapid advancement of energy-efficient parallel ultra-low-power (ULP) µcontrollers units (MCUs) is enabling the development of autonomous nano-sized unmanned aerial vehicles (nano-UAVs). These sub-10cm drones represent the next generation of unobtrusive robotic helpers and ubiquitous smart sensors. However, nano-UAVs face significant power and payload constraints while requiring advanced computing capabilities akin to standard drones, including real-time Machine Learning (ML) performance and the safe co-existence of general-purpose and real-time OSs. Although some advanced parallel ULP MCUs offer the necessary ML computing capabilities within the prescribed power limits, they rely on small main memories (<1MB) and µcontroller-class CPUs with no virtualization or security features, and hence only support simple bare-metal runtimes. In this work, we present Shaheen, a 9mm 2 200mW SoC implemented in 22nm FDX technology. Differently from state-of-the-art MCUs, Shaheen integrates a Linux-capable RV64 core, compliant with the v1.0 ratified Hypervisor extension and equipped with timing channel protection, along with a low-cost and low-power memory controller exposing up to 512MB of off-chip low-cost low-power HyperRAM directly to the CPU. At the same time, it integrates a fully programmable energy-and area-efficient multi-core cluster of RV32 cores optimized for general-purpose DSP as well as reduced-and mixed-precision ML. To the best of the authors' knowledge, it is the first silicon prototype of a ULP SoC coupling the RV64 and RV32 cores in a heterogeneous host+accelerator architecture fully based on the RISC-V ISA. We demonstrate the capabilities of the proposed SoC on a wide range of benchmarks relevant to nano-UAV applications including general-purpose DSP as well as inference and online learning of quantized DNNs. The cluster can deliver up to 90GOp/s and up to 1.8TOp/s/W on 2-bit integer kernels and up to 7.9GFLOp/s and up to 150GFLOp/s/W on 16-bit FP kernels.

Area and Power Efficient Implementation of Configurable Ring Oscillator PUF

“…The proposed design was implemented in 22nm FDSOI technology using the Synopsys tools. The proposed PUF has been taped out as part of RISC-V based SOC reported in [15] and shown in Fig. 3.…”

“Interrupting” the Status Quo: A First Glance at the RISC-V Advanced Interrupt Architecture (AIA)

“…This is justified by (i) the additional functionalities offered by 5 There may be deviations in hardware cost assessment between FPGA and ASIC synthesis. We plan to conduct this study in future work by integrating our AIA IP into an evolving version of Shaheen [15].…”

“…To carry out this study, we first developed a parametrizable Advanced Platform-Level Interrupt Controller (APLIC) IP and an Incoming Message-Signaled Interrupt Controller (IMSIC) IP -which together form the AIA IP -fully compliant with the RISC-V AIA specification v1.0. These IPs were integrated into a CVA6-based SoC with virtualization support [15]. Then, we explore alternative designs and microarchitectural enhancements for the implemented IP to cope with the MCS requirements (e.g., real-time and predictability).…”