HPS, a new microarchitecture: rationale and introduction

Patt, Yale N.; Hwu, Wen mei; Shebanow, Michael

doi:10.1145/18927.18916

Cited by 93 publications

(7 citation statements)

References 6 publications

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“…The machine model simulated is the HPS microarchitecture [9] [lo]. HPS is a wide-issue out-of-order execution machine, using Tomasulo algorithm for dynamic schcduling [12].…”

Section: Experimental Methodologymentioning

confidence: 99%

Target prediction for indirect jumps

Chang¹,

Hao²,

Patt³

1997

Proceedings of the 24th Annual International Symposium on Computer Architecture

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As the issue rate and pipeline depth of high performance superscalar processors increase, the amount of speculative work issued also increases. Because speculative work must be thrown away in the event of a branch misprediction, wide-issue, deeply pipelined processors must employ accurate branch predictors to effectively exploit their performance potential. Many existing branch prediction schemes are capable of accurately predicting the direction of conditional branches. However, these schemes are ineffective in predicting the targets of indirect jumps achieving, on average, a prediction accuracy rate of 51.8% for the SPECmt95 benchmarks.In this paper, we propose a new prediction mechanism, the target cache, for predicting indirect jump targets. For the per1 and gee benchmarks, thii mechanism reduces the indirect jump misprediction rate by 93.4% and 63.3% and the overall execution time by 14% and 5%. *Although return instructions technically are indirect jumps, they are not handled with the target cache because they are effcctivoly handled with the return address stnck (13, 41.

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“…The machine model simulated is the HPS microarchitecture [9] [lo]. HPS is a wide-issue out-of-order execution machine, using Tomasulo algorithm for dynamic schcduling [12].…”

Section: Experimental Methodologymentioning

confidence: 99%

Target prediction for indirect jumps

Chang¹,

Hao²,

Patt³

1997

Proceedings of the 24th Annual International Symposium on Computer Architecture

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“…The algorithm was first used in the ftoating point unit of the IBM 360/91 and is currently being used for the entire execution unit in the HPS project at Berkeley [19]. The Tomasulo algorithm is not applied to the write-once registers in the PUP.…”

Section: An Implementation Of the Pupmentioning

confidence: 99%

PUP: An Architecture to Exploit Parallel Unification in Prolog

Chen¹,

Singhal²,

Patt³

1988

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“…The prediction is verified when the outcome of the event is known, and corrective action is taken if the prediction was wrong. Speculative execution has been successfully used to overcome performance hurdles in a variety of scenarios, for example, branch instructions (control speculation) [34,40], ambiguous dependences (dependence speculation) [30], parallelization (speculative parallelization) [41], and locking overheads (speculative lock elision) [35].…”

Section: Introductionmentioning

confidence: 99%

Coherence decoupling

Huh

Chang

Burger

et al. 2004

SIGOPS Oper. Syst. Rev.

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This paper explores a new technique called coherence decoupling, which breaks a traditional cache coherence protocol into two protocols: a Speculative Cache Lookup (SCL) protocol and a safe, backing coherence protocol. The SCL protocol produces a speculative load value, typically from an invalid cache line, permitting the processor to compute with incoherent data. In parallel, the coherence protocol obtains the necessary coherence permissions and the correct value. Eventually, the speculative use of the incoherent data can be verified against the coherent data. Thus, coherence decoupling can greatly reduce -if not eliminate -the effects of false sharing. Furthermore, coherence decoupling can also reduce latencies incurred by true sharing. SCL protocols reduce those latencies by speculatively writing updates into invalid lines, thereby increasing the accuracy of speculation, without complicating the simple, underlying coherence protocol that guarantees correctness.The performance benefits of coherence decoupling are evaluated using a full-system simulator and a mix of commercial and scientific benchmarks. Our results show that 40% to 90% of all coherence misses can be speculated correctly, and therefore their latencies partially or fully hidden. This capability results in performance improvements ranging from 3% to over 16%, in most cases where the latencies of coherence misses have an effect on performance.

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HPS, a new microarchitecture: rationale and introduction

Cited by 93 publications

References 6 publications

Target prediction for indirect jumps

Target prediction for indirect jumps

PUP: An Architecture to Exploit Parallel Unification in Prolog

Coherence decoupling

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