Proceedings of the 24th Annual International Symposium on Computer Architecture 1997
DOI: 10.1145/264107.264209
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Target prediction for indirect jumps

Abstract: As the issue rate and pipeline depth of high performance superscalar processors increase, the amount of speculative work issued also increases. Because speculative work must be thrown away in the event of a branch misprediction, wide-issue, deeply pipelined processors must employ accurate branch predictors to effectively exploit their performance potential. Many existing branch prediction schemes are capable of accurately predicting the direction of conditional branches. However, these schemes are ineffective … Show more

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Cited by 95 publications
(39 citation statements)
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“…Techniques to reduce the impact of I-cache misses include multi-level instruction memory hierarchies [12] and instruction prefetch [28]. Techniques to reduce the impact of branch mispredictions include hybrid [17] and indirect [8] branch predictors, and recovery miss caches to reduce misprediction latencies [4]. A number of compiler-based techniques work to improve instruction delivery performance.…”
Section: Related Fetch Bandwidth Researchmentioning
confidence: 99%
“…Techniques to reduce the impact of I-cache misses include multi-level instruction memory hierarchies [12] and instruction prefetch [28]. Techniques to reduce the impact of branch mispredictions include hybrid [17] and indirect [8] branch predictors, and recovery miss caches to reduce misprediction latencies [4]. A number of compiler-based techniques work to improve instruction delivery performance.…”
Section: Related Fetch Bandwidth Researchmentioning
confidence: 99%
“…However, the execution path of a branch cannot be easily resolved in advance. Thus, branches typically cause delays in the pipeline [14][15][16][17].…”
Section: Branch Target Buffer (Btb) Support For Branches and Indirectmentioning
confidence: 99%
“…Various pieces of information can be kept in the BTB, including tags associated with the branch address, the branch target address, and branch prediction information [15]. However, it has been reported that BTBbased prediction schemes perform poorly for indirect jumps, since the target of an indirect jump can change with every dynamic instance of that branch [14,16]. In fact, some compilers provide techniques that insert extra conditional branches that check for likely targets to avoid the execution of indirect jumps from a table [18] or indirect calls [19].…”
Section: Branch Target Buffer (Btb) Support For Branches and Indirectmentioning
confidence: 99%
“…There are few solutions to this problem and all of them involve a great deal of further work. One of the most recent valuable approaches in this sense, improves the indirect jumps prediction accuracy by choosing its target from the most recent targets of the indirect jump that have already been encountered [Cha97], based on a simply heuristic. In contrast, our new approach proposes that the NN that predicts the branch direction also predict the target effective address, for indirect jumps only, based on the same information: PC, HRg and HRl (Figure 2).…”
Section: Vl(t+1) = Vl(t) (4)mentioning
confidence: 99%
“…Our work hypothesis will consider branch prediction as a particular problem belonging to pattern recognition class and therefore, we consider it's desirable to use neural networks in order to predict branches. Also, we investigate comparatively, through a trace driven simulation method, a classical branch prediction scheme proceeded from Professor Yale Patt's research group [Yeh92,Cha97,Eve96] with some modifications and the proposed neural branch predictor, both of them integrated into a MII environment. We used the traces obtained based on the eight C Stanford integer benchmarks.…”
Section: Introductionmentioning
confidence: 99%