How Persistent Memory Will Change Software Systems

Badam, Anirudh

doi:10.1109/mc.2013.189

Cited by 21 publications

(13 citation statements)

References 14 publications

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“…This figure shows the fraction of memory access cycles that are spent due to delays related to bus turnaround between reads and writes as a function of the number of write queue entries. 5 The figure shows that up to 17% of memory bus cycles are wasted due to frequent bus turnarounds, with a commonly-used 64-entry write queue. We found that this is mainly because persistent writes frequently overflow the write queue and force the memory controller to drain the writes.…”

Section: Inefficiency Of Prior Memory Scheduling Schemesmentioning

confidence: 99%

“…1 As it is in its early stages of development, persistent memory especially serves applications that can benefit from reducing storage (or, persistent data) access latency with relatively few or lightweight changes to application programs, system software, and hardware [7]. Such applications include databases [90], file systems [14,29], keyvalue stores [13], and persistent file caches [5,7]. Other types of applications may not directly benefit from persistent memory, but can still use BA-NVMs as their working memory (nonvolatile main memory without persistence) to leverage the benefits of large capacity and low stand-by power [45,73].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

Zhao

Mutlu²,

Xie

2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-Byte-addressable nonvolatile memories promise a new technology, persistent memory, which incorporates desirable attributes from both traditional main memory (byte-addressability and fast interface) and traditional storage (data persistence). To support data persistence, a persistent memory system requires sophisticated data duplication and ordering control for write requests. As a result, applications that manipulate persistent memory (persistent applications) have very different memory access characteristics than traditional (non-persistent) applications, as shown in this paper. Persistent applications introduce heavy write traffic to contiguous memory regions at a memory channel, which cannot concurrently service read and write requests, leading to memory bandwidth underutilization due to low bank-level parallelism, frequent write queue drains, and frequent bus turnarounds between reads and writes. These characteristics undermine the high-performance and fairness offered by conventional memory scheduling schemes designed for non-persistent applications.Our goal in this paper is to design a fair and high-performance memory control scheme for a persistent memory based system that runs both persistent and non-persistent applications. Our proposal, FIRM, consists of three key ideas. First, FIRM categorizes request sources as non-intensive, streaming, random and persistent, and forms batches of requests for each source. Second, FIRM strides persistent memory updates across multiple banks, thereby improving bank-level parallelism and hence memory bandwidth utilization of persistent memory accesses. Third, FIRM schedules read and write request batches from different sources in a manner that minimizes bus turnarounds and write queue drains. Our detailed evaluations show that, compared to five previous memory scheduler designs, FIRM provides significantly higher system performance and fairness.

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Section: Inefficiency Of Prior Memory Scheduling Schemesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

Zhao

Mutlu²,

Xie

2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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“…Byte-addressable NVRAM can harbor data in a persistent manner while providing access latency comparable to that of DRAM [6,30]. Table 1 compares conventional storage and memory to NVRAMs such as PCRAM, RRAM, and MRAM.…”

Section: Non-volatile Rammentioning

confidence: 99%

LASER: Latency-Aware Segment Relocation for non-volatile memory

Kim

Lee

Shin³

et al. 2015

Journal of Systems Architecture

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“…Two articles in the August 2013 issue of this magazine cover the impact of these storage-memory improvement technologies on software systems. 7,8 Solutions for working memory are more difficult to predict because of its stricter performance requirements. In the short term, we believe that HMC arrays are likely to be adopted in server markets due to their increased performance.…”

Section: Impact Of Alternative Technologiesmentioning

confidence: 99%