HotSpot: a dynamic compact thermal model at the processor-architecture level

Stan, Mircea R.; Skadron, Kevin; Barcella, Marco; Huang, Wei; Sankaranarayanan, Karthik; Velusamy, Sivakumar

doi:10.1016/s0026-2692(03)00206-4

Cited by 91 publications

(56 citation statements)

References 9 publications

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“…This modeling approach improves our previous work [16] and makes it fully parameterized and satisfy most of the above desirable features as shown later in the paper. 1 The paper is organized as follows.…”

Section: ) Computational Speedsupporting

confidence: 52%

Parameterized physical compact thermal modeling

Huang

Stan

Skadron

2005

IEEE Trans. Comp. Packag. Technol.

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Abstract-This paper presents a compact thermal modeling approach, which is fully parameterized according to design geometries and material physical properties. While most compact modeling approaches facilitate thermal characterization of existing package designs, our method is better suited for preliminary exploration of the design space at both the silicon level and the package level. We show that our modeling method achieves reasonable boundary condition independence (BCI) by comparing an example compact thermal model with a BCI model for a benchmark BGA single-chip package under the same standard set of boundary conditions. In essence, the presented compact thermal modeling method can act as a convenient medium for enhanced interactions and collaborations among designers at the package, circuit and computer architecture levels, leading to efficient early evaluations of different thermally-related design trade-offs at all the above levels of abstraction before the actual detailed design is available. The presented modeling method can be easily extended to model emerging packaging schemes such as stacked chip-scale packaging (SCP) and 3-D integration.Index Terms-compact thermal model, boundary condition independence (BCI), package design, parametrization, temperature.

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Section: ) Computational Speedsupporting

confidence: 52%

Parameterized physical compact thermal modeling

Huang

Stan

Skadron

2005

IEEE Trans. Comp. Packag. Technol.

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“…The RF shows the highest power density as it has a severe access frequency and occupies a relatively small area. As a result, due to high areal power density, the RF is known to the hottest unit in the microprocessor [62].…”

Section: Staticmentioning

confidence: 99%

An Overview of Architecture-Level Power- and Energy-Efficient Design Techniques

Ratkovic¹,

Bezanic²,

Ünsal³

et al. 2015

Advances in Computers

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“…extremely high power densities). In this paper, we extend the discussions in [4] to analyze the sources of inaccuracies for the by-construction compact thermal modeling approach and provide solutions to improve the accuracy even under the aforementioned extreme conditions, which is an important improvement of our previous work [3], [10], [13].…”

Section: Related Workmentioning

confidence: 86%

Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model

Huang

Sankaranarayanan

Skadron

et al. 2008

IEEE Trans. Comput.

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Abstract-Preventing silicon chips from negative, even disastrous thermal hazards has become increasingly challenging these days; considering thermal effects early in the design cycle is thus required. To achieve this, an accurate yet fast temperature model together with an early-stage, thermally optimized, design flow are needed. In this paper, we present an improved block-based compact thermal model (HotSpot 4.0) that automatically achieves good accuracy even under extreme conditions. The model has been extensively validated with detailed finite-element thermal simulation tools. We also show that properly modeling package components and applying the right boundary conditions are crucial to making full-chip thermal models like HotSpot accurately resemble what happens in the real world. Ignoring or oversimplifying package components can lead to inaccurate temperature estimations and potential thermal hazards that are costly to fix in later designs stages. Such a full-chip and package thermal model can then be incorporated into a thermally optimized design flow where it acts as an efficient communication medium among computer architects, circuit designers and package designers in early microprocessor design stages, to achieve early and accurate design decisions and also faster design convergence. For example, the temperature-leakage interaction can be readily analyzed within such a design flow to predict potential thermal hazards such as thermal runaway. An example SoC design illustrates the importance of adopting such a thermally optimized design flow in early design stages.Index Terms-compact thermal model, early design stages, leakage, parameterized model, temperature, thermally optimized design flow.

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HotSpot: a dynamic compact thermal model at the processor-architecture level

Cited by 91 publications

References 9 publications

Parameterized physical compact thermal modeling

Parameterized physical compact thermal modeling

An Overview of Architecture-Level Power- and Energy-Efficient Design Techniques

Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model

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