Parameterized physical compact thermal modeling

Abstract

Abstract-This paper presents a compact thermal modeling approach, which is fully parameterized according to design geometries and material physical properties. While most compact modeling approaches facilitate thermal characterization of existing package designs, our method is better suited for preliminary exploration of the design space at both the silicon level and the package level. We show that our modeling method achieves reasonable boundary condition independence (BCI) by comparing an example compact thermal model with a BCI model for a benchmark BGA single-chip package under the same standard set of boundary conditions. In essence, the presented compact thermal modeling method can act as a convenient medium for enhanced interactions and collaborations among designers at the package, circuit and computer architecture levels, leading to efficient early evaluations of different thermally-related design trade-offs at all the above levels of abstraction before the actual detailed design is available. The presented modeling method can be easily extended to model emerging packaging schemes such as stacked chip-scale packaging (SCP) and 3-D integration.Index Terms-compact thermal model, boundary condition independence (BCI), package design, parametrization, temperature.

Thermally-Aware Design

“…If isothermal boundary conditions are to be used, this simply implies that the node(s) connected to the ambient correspond to the ground node. On the other hand, it is possible to use a more detailed thermal model for the package and heat spreader, consisting of an interconnection of thermal resistors and thermal capacitors, as used in HotSpot, [8][9][10][11][12][13][14] or another type of compact model such as a reduced-order model. In either case, one or more nodes of the package model will be connected to the ambient, which is taken to be the ground node.…”

Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model

“…There are also other thermal models dividing silicon into fine meshes and solving with fast solvers, such as [8], [9] and the HotSpot grid model [10]. These models also achieve excellent accuracy whereas still incurring significant computational overhead compared to the parameterized compact thermal models such as the HotSpot block model [2], [3]. On the other hand, the compact thermal models trade off absolute accuracy with simpler structure and speed by constructing the model directly according to functional units of interest and physical properties of the chip.…”

“…Such a thermal model should be "by-construction" and parameterized, i.e., the model is constructed solely based on chip and package geometries and material properties, hence allowing a designer to explore potential design choices without the costly, slow building of a prototype [2].…”

Exploring Temperature-Aware Design of Memory Architectures in VLIW Systems

“…All these models have detailed temperature distribution across the silicon die and can that be solved efficiently. However, it has been reported recently that the results achieved by these models present inaccuracy problems [6,7]. All these works provide an analytical method for studying the thermal distribution in the die of high performance processors but they require the complete knowledge of the layout details.…”