1987
DOI: 10.1109/t-ed.1987.23004
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Hot-electron-induced punchthrough (HEIP) effect in submicrometer PMOSFET's

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Cited by 127 publications
(25 citation statements)
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“…2 The small gain at the initial and turnaround at the further stress are explicitly expressed in all the parameter curves. This initial phenomenon called HEIP is known to originate from electron trapping in PMOSFETs, where a negative oxide charge is created at the drain side of the device by secondary electrons injected over the silicon-oxide potential barrier and trapped at oxide defects [7]. At longer stress time, HEIP phenomenon disappears and degradation behavior becomes similar such as raised V th , lessened gm max and I d,sat to those shown for the MS and HS stressed devices.…”
Section: Resultsmentioning
confidence: 98%
See 1 more Smart Citation
“…2 The small gain at the initial and turnaround at the further stress are explicitly expressed in all the parameter curves. This initial phenomenon called HEIP is known to originate from electron trapping in PMOSFETs, where a negative oxide charge is created at the drain side of the device by secondary electrons injected over the silicon-oxide potential barrier and trapped at oxide defects [7]. At longer stress time, HEIP phenomenon disappears and degradation behavior becomes similar such as raised V th , lessened gm max and I d,sat to those shown for the MS and HS stressed devices.…”
Section: Resultsmentioning
confidence: 98%
“…recognized in PMOS degradation that V th decreases are accompanied by I ds,sat increase [7]. Therefore, the parameter fit at LS stressed device was only performed with small data points of long time stress, which could cause some error for exponent estimation.…”
Section: Resultsmentioning
confidence: 99%
“…Thus, effective channel length (L ch ) and threshold voltage (V th ) vary as shown in Fig. 1 [6]. It leads to the variation of on-current, off-current, circuit performance and power consuption [7,8].…”
Section: Introductionmentioning
confidence: 99%
“…However, aggressive scaling of the gate lengths has rendered hot carrier injection (HCI) induced performance degradation of pMOSFETs comparable to that of nMOSFETs [12]. For relatively long channel submicron pFETs (L P 0.35 lm) the worst case stress (WCS) conditions and the degradation mechanisms have long been established.…”
Section: Introductionmentioning
confidence: 99%
“…Electrons that are avalanche generated in the pinch off region may get injected and trapped into the gate oxide near the drain. The negative charges lead to a reduction of the absolute value of the threshold voltage and an effective channel shortening [12].…”
Section: Introductionmentioning
confidence: 99%