Hot-electron-induced input offset voltage degradation in CMOS differential amplifiers

Mohamedi, S.Z.; Chan, V. W. S.; Park, J.-T.; Nouri, F.; Scharf, B.; Chung, J.E.

doi:10.1109/relphy.1992.187626

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Differential Stage Circuit1

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Cited by 15 publications

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“…It is either an improvement of the offset (sample #2) or a serious degradation (sample #4). Hot-electron-induced input offset voltage degradation is a well-known phenomenon in CMOS differential stages [10][11].…”

Section: Differential Stage Circuitmentioning

confidence: 99%

ESD induced latent defects in CMOS ICs and reliability impact

Guitard¹,

Trémouilles²,

Alves³

et al. 2004

2004 Electrical Overstress/Electrostatic Discharge Symposium

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A dedicated test vehicle was designed to study the impact of ESD induced latent defects on digital and analog CMOS circuits. Both CDM and TLP stresses were applied to these circuits through a specific pad which allows stressing the circuit core. Both electrical characterization and non-destructive failure analysis were performed to locate the induced defect. For digital circuits, functionality is not affected although the IDDQ quiescent current increased. However, after burn-in and storage, it was observed that the IDDQ current significantly increased suggesting that the circuit lifetime is degraded. In contrast, even at very low stress level, the analog circuit exhibits a dramatic offset degradation and no recovery is observed after burn-in.

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Section: Differential Stage Circuitmentioning

confidence: 99%