Hot carrier reliability for 0.13 μm CMOS technology with dual gate oxide thickness

Lin, Cuiying; Biesemans, S.; Han, Liang; Houlihan, K.; Schiml, T.; Schruefer, K.; Wann, C.; Chen, J.; Mahnkopf, R.

doi:10.1109/iedm.2000.904276

Cited by 18 publications

(15 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Thus, the WCC for the devices of this class are realized when the carrier flux is maximal. For LV n-MOSFETs as well as for p-MOSFETs this scenario corresponds to the equality of the source-drain and gate voltages (V gs = V ds ) [10][11][12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

“…There is a considerable number of papers published in the literature devoted to the detailed analysis of hot-carrier degradation worst-case conditions for long-channel and/or high voltage transistors as well as for scaled low voltage devices employed in logic applications [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20]. These papers provide us with a rather detailed experimental study of this matter, but the reliable microscopic picture of the problem is still missing.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Analysis of worst-case hot-carrier conditions for high voltage transistors based on full-band monte-carlo simulations

Starkov

Tyaginov

Triebl

et al. 2010

2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits

View full text Add to dashboard Cite

Using a physics-based model for hot-carrier degradation we analyze the worst-case conditions for long-channel transistors of two types: a relatively low voltage n-MOSFET and a highvoltage p-LDMOS. The key issue in the hot-carrier degradation model is the information about the carrier energetical distribution function which allows us to asses the carrier acceleration integral determining the interface state build-up and which controls the interplay between the single-and multiple-carrier mechanisms of Si-H bond rupture. To analyze the worst-case conditions we generate intensity maps, i.e. dependences of some crucial quantities on source-drain Vds and gate Vgs stress voltage. These quantities are the boundary of the high-energy tail of the energy distribution function, the interface state generation rate and the total dose of degradation. The difference between positions of severest degradation spots evaluated according different criteria is also plotted as a function of stress voltages. Using these maps we demonstrate that the worst-case conditions are realized at 0.4Vds < Vgs < 0.5Vds for the n-MOSFET and at the maximal gate current for p-LDMOS. These findings correspond to experimental results published in the literature.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analysis of worst-case hot-carrier conditions for high voltage transistors based on full-band monte-carlo simulations

Starkov

Tyaginov

Triebl

et al. 2010

2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits

View full text Add to dashboard Cite

show abstract

“…Many studies focused on the electrical characterization and the understanding of transistors with a dual gate SiO 2 oxide in logic devices such as a system-on-a-chip. 4,5 However, little is known regarding the electrical and physical characteristics of high-k gate oxide MOS capacitors with a dual thickness and their fabrication processes.…”

Section: Introductionmentioning

confidence: 99%

The electrical and physical analysis of Pt gate/Al2O3/p-Si (100) with dual high-k gate oxide thickness for deep submicron complementary metal-oxide-semiconductor device with low power and high reliability

Lee

Eom

et al. 2005

Journal of Elec Materi

View full text Add to dashboard Cite

In order to examine the electrical and physical properties of Al 2 O 3 layers with dual thickness on a chip, Pt gate/Al 2 O 3 with dual thickness/p-type Si (100) samples were fabricated using atomic-layer deposition, separation photolithography, and 100:1 HF wet etching to remove the first Al 2 O 3 layer. Dual metal-oxide-semiconductor (MOS) capacitors with thin (physical thickness, ϳ4.5 nm, equivalent oxide thicknesses (EOT): 2.8 nm) and thick (physical thickness, ϳ8.2 nm, EOT: 4.3 nm) Al 2 O 3 layers showed a good leakage current density of Ϫ5.4 ϫ 10 Ϫ6 A/cm 2 and Ϫ2.5 ϫ 10 Ϫ9 A/cm 2 at Ϫ1 V, respectively; good reliability characteristics as a result of the good surface roughness; low capacitance versus voltage measurements (C-V) hysteresis; and a good interface state density (ϳ7 ϫ 10 10 cm Ϫ2 eV Ϫ1 near the midgap) as a result of pre-rapid thermal annealing (pre-RTA) after depositing the Al 2 O 3 layer compared with the single MOS capacitors without the pre-RTA. These results suggest that dual Al 2 O 3 layers using the dual gate oxide (DGOX) process can be used for the simultaneous integration of the low power transistors with a thin Al 2 O 3 layer and high reliability regions with a thick Al 2 O 3 layer.

show abstract

“…During HCS, the maximum substrate current (I sub ) introduces interface states (N it ) and oxide traps (N ot ) close to the drain junction [1]. These N it and N ot generated by hot electron emission degrades the MOSFET channel near the drain.…”

Section: Introductionmentioning

confidence: 99%

Hot Carrier Degradation and Performance of 65nm RF n-MOSFET

Fakhruddin

Tang

Kuo

et al. 2007

2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium

View full text Add to dashboard Cite

Hot carrier stress (HCS) induces significant degradation on the performance of 65nm RF n-MOSFET with minimum poly length (L poly ). Although the cutoff frequency (F t ) is very high (~212 GHz) for these devices, the high HCS degradation poses a challenge for RF application. Additional effort will be needed to improve the process and/or device to take full advantage of the record n-MOSFET performance.

show abstract

Hot carrier reliability for 0.13 μm CMOS technology with dual gate oxide thickness

Cited by 18 publications

References 0 publications

Analysis of worst-case hot-carrier conditions for high voltage transistors based on full-band monte-carlo simulations

Analysis of worst-case hot-carrier conditions for high voltage transistors based on full-band monte-carlo simulations

The electrical and physical analysis of Pt gate/Al2O3/p-Si (100) with dual high-k gate oxide thickness for deep submicron complementary metal-oxide-semiconductor device with low power and high reliability

Hot Carrier Degradation and Performance of 65nm RF n-MOSFET

Contact Info

Product

Resources

About