Hot-Carrier Effects

Hu, Chenming

doi:10.1016/b978-0-12-234118-2.50007-3

Cited by 44 publications

(15 citation statements)

References 56 publications

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“…Significant efforts have been focused for decades on understanding the degradation mechanisms, HCI models and the impact of hot carrier on circuits [1] [2] [3]. Various suppression techniques have been proposed in [4], [5], [6] and [7] to enhance device hot carrier immunity.…”

Section: Introductionmentioning

confidence: 99%

Optimization of hot carrier resistance for 0.18µm CMOS technology

Ching¹,

Sun²,

Ping³

2008

2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)

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With the further scaling down of CMOS devices, hot carrier induced degradation has become one of the most important reliability concerns. In the hot carrier effect carriers are accelerated by the channel electric fields and become trapped in the oxide. TIlese trapped charges cause time dependent shifts in measured device parameters. In time, substantial device parameter degradation can occur, resulting in device failure. Studies have been carried out to enhance device hot carrier immunity by reducing and departure the high electrical field from the drain area. TIle evaluations were focused on the implant energy and dose factors in order to achieve more graded device junction. TIle substantial result shows 10 times improvement in hot carrier injection (HCI) DC lifetime and reveals a good direction for suppression the hot carrier effects in 0. 181lm CMOS teclmology.

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Section: Introductionmentioning

confidence: 99%

Optimization of hot carrier resistance for 0.18µm CMOS technology

Ching¹,

Sun²,

Ping³

2008

2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)

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“…For comparison, we h a ve a l s o included in the table a lower bound on the number of bu ers, which is the minimum number of bu ers needed to meet the load cap constraints while disregarding bu er skew constraints. 5 In all but one case, the lower bound is matched by the optimum bu ering with = 4, and often it is matched with a bu er skew as small as 2.…”

Section: Dynamic Programming Algorithmmentioning

confidence: 99%

Practical Approximation Algorithms for Separable Packing Linear Programs

Dragan

Kahng

Măndoiu

et al. 2001

Lecture Notes in Computer Science

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Abstract|Bounding the load capacitance at gate outputs is a standard element i n t o d a y's electrical correctness methodologies for high-speed digital VLSI design. Bounds on load caps improve coupling noise immunity, reduce degradation of signal transition edges, and reduce delay uncertainty due to coupling noise 6 . For clock and test distribution, an additional design requirement is bounding the bu er skew, i.e., the di erence between the maximum and the minimum number of bu ers over all source-to-sink paths in the routing tree, since bu er skew is one of the main factors a ecting sink delay s k ew 10 . In this paper we consider algorithms for bu ering a given tree with the minimum number of bu ers under given load cap and bu er skew constraints. We show that the greedy algorithm proposed by T ellez and Sarrafzadeh 10 is suboptimal for non-zero bu er skew bounds and give examples showing that no bottom-up greedy algorithm can achieve optimality. The main contribution of the paper is an optimal dynamic programming algorithm for the problem. Experiments on test cases extracted from recent industrial designs show that the dynamic programming algorithm has practical running time and inserts up to 5 10 fewer bu ers compared to the algorithm in 10 . I IntroductionFor high-speed digital VLSI design, bounding the load capacitance at gate outputs is a standard element i n t oday's electrical correctness methodologies. Bounds on load caps improve coupling noise immunity, reduce degradation of signal transition edges, and reduce delay uncertainty due to coupling noise 6 . 1 According to 9 , commercial EDA methodologies and tools for signal integrity rely heavily on upper-bounding the capacitive loads on This work was partially supported by Cadence Design Systems, Inc., the MARCO Gigascale Silicon Research C e n ter and NSF Grant CCR-9988331.1 Such bounds also improve reliability with respect to hot-carrier oxide breakdown hot electrons 4, 5 and AC self-heating in interconnects 8 , and facilitate technology migration since designs are more balanced. driver and bu er outputs to prevent v ery long slew times on signal transitions. Essentially, the load capacitance bounds serve a s proxies for bounds on input rise fall times at bu ers and sinks Tellez and Sarrafzadeh 10 formally prove t h i s equivalence using a simple linear model. We assume that such capacitive load bounds are inherent t o any bu ered routing tree design task. It is natural to propose a minimum-bu er formulation, so as to minimize changes made to the routing tree in meeting the load bounds.Bu ering to control slew times is also critical to early timing analysis. With lookup-table based modeling of gate delays and output transition times, very long input slews tend to be propagated inaccurately, resulting in extremely slow transitions. Static timing analyses that are based on the associated delay calculations will be utterly compromised, and useless for driving performance optimizations. Thus, early timing analysis must start with a bu ering solution that...

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“…Although slew time is not completely determined by capacitive loads, Tellez and Sarrafzadeh [24] show experimentally the strong correlation between them. Bounded capacitive loads also improve reliability with respect to hot-carrier oxide breakdown (hot electrons) [10], [12] and AC self-heating in interconnects [20], and facilitate technology migration since designs are more balanced.…”

Section: Introductionmentioning

confidence: 99%

Minimum buffered routing with bounded capacitive load for slew rate and reliability control

Alpert

Kahng

Liu

et al. 2003

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In high-speed digital VLSI design, bounding the load capacitance at gate outputs is a well-known methodology to improve coupling noise immunity, reduce degradation of signal transition edges, and reduce delay uncertainty due to coupling noise. Bounding load capacitance also improves reliability with respect to hot-carrier oxide breakdown and AC self-heating in interconnects, and guarantees bounded input rise/fall times at buffers and sinks.This paper introduces a new minimum-buffer routing problem (MBRP) formulation which requires that the capacitive load of each buffer, and of the source driver, be upper-bounded by a given constant. Our contributions are as follows:• We give linear-time algorithms for optimal buffering of a given routing tree with a single (inverting or noninverting) buffer type. • For simultaneous routing and buffering with a single noninverting buffer type, we prove that no algorithm can guarantee a factor smaller than 2 unless P = NP and give an algorithm with approximation factor slightly larger than 2 for typical buffers. For the case of a single inverting buffer type, we give an algorithm with approximation factor slightly larger than 4.• We give local-improvement and clustering based MBRP heuristics with improved practical performance, and present a comprehensive experimental study comparing the runtime/quality tradeoffs of the proposed MBRP heuristics on test cases extracted from recent industrial designs.

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Hot-Carrier Effects

Cited by 44 publications

References 56 publications

Optimization of hot carrier resistance for 0.18µm CMOS technology

Optimization of hot carrier resistance for 0.18µm CMOS technology

Practical Approximation Algorithms for Separable Packing Linear Programs

Minimum buffered routing with bounded capacitive load for slew rate and reliability control

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Hot-Carrier Effects

Cited by 44 publications

References 56 publications

Optimization of hot carrier resistance for 0.18&#x00B5;m CMOS technology

Optimization of hot carrier resistance for 0.18&#x00B5;m CMOS technology

Practical Approximation Algorithms for Separable Packing Linear Programs

Minimum buffered routing with bounded capacitive load for slew rate and reliability control

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Optimization of hot carrier resistance for 0.18µm CMOS technology

Optimization of hot carrier resistance for 0.18µm CMOS technology