Abstract|Bounding the load capacitance at gate outputs is a standard element i n t o d a y's electrical correctness methodologies for high-speed digital VLSI design. Bounds on load caps improve coupling noise immunity, reduce degradation of signal transition edges, and reduce delay uncertainty due to coupling noise 6 . For clock and test distribution, an additional design requirement is bounding the bu er skew, i.e., the di erence between the maximum and the minimum number of bu ers over all source-to-sink paths in the routing tree, since bu er skew is one of the main factors a ecting sink delay s k ew 10 . In this paper we consider algorithms for bu ering a given tree with the minimum number of bu ers under given load cap and bu er skew constraints. We show that the greedy algorithm proposed by T ellez and Sarrafzadeh 10 is suboptimal for non-zero bu er skew bounds and give examples showing that no bottom-up greedy algorithm can achieve optimality. The main contribution of the paper is an optimal dynamic programming algorithm for the problem. Experiments on test cases extracted from recent industrial designs show that the dynamic programming algorithm has practical running time and inserts up to 5 10 fewer bu ers compared to the algorithm in 10 .
I IntroductionFor high-speed digital VLSI design, bounding the load capacitance at gate outputs is a standard element i n t oday's electrical correctness methodologies. Bounds on load caps improve coupling noise immunity, reduce degradation of signal transition edges, and reduce delay uncertainty due to coupling noise 6 . 1 According to 9 , commercial EDA methodologies and tools for signal integrity rely heavily on upper-bounding the capacitive loads on This work was partially supported by Cadence Design Systems, Inc., the MARCO Gigascale Silicon Research C e n ter and NSF Grant CCR-9988331.1 Such bounds also improve reliability with respect to hot-carrier oxide breakdown hot electrons 4, 5 and AC self-heating in interconnects 8 , and facilitate technology migration since designs are more balanced. driver and bu er outputs to prevent v ery long slew times on signal transitions. Essentially, the load capacitance bounds serve a s proxies for bounds on input rise fall times at bu ers and sinks Tellez and Sarrafzadeh 10 formally prove t h i s equivalence using a simple linear model. We assume that such capacitive load bounds are inherent t o any bu ered routing tree design task. It is natural to propose a minimum-bu er formulation, so as to minimize changes made to the routing tree in meeting the load bounds.Bu ering to control slew times is also critical to early timing analysis. With lookup-table based modeling of gate delays and output transition times, very long input slews tend to be propagated inaccurately, resulting in extremely slow transitions. Static timing analyses that are based on the associated delay calculations will be utterly compromised, and useless for driving performance optimizations. Thus, early timing analysis must start with a bu ering solution that...