Minimum buffered routing with bounded capacitive load for slew rate and reliability control

Abstract

Abstract-In high-speed digital VLSI design, bounding the load capacitance at gate outputs is a well-known methodology to improve coupling noise immunity, reduce degradation of signal transition edges, and reduce delay uncertainty due to coupling noise. Bounding load capacitance also improves reliability with respect to hot-carrier oxide breakdown and AC self-heating in interconnects, and guarantees bounded input rise/fall times at buffers and sinks.This paper introduces a new minimum-buffer routing problem (MBRP) formulation which requires that the capacitive load of each buffer, and of the source driver, be upper-bounded by a given constant. Our contributions are as follows:• We give linear-time algorithms for optimal buffering of a given routing tree with a single (inverting or noninverting) buffer type. • For simultaneous routing and buffering with a single noninverting buffer type, we prove that no algorithm can guarantee a factor smaller than 2 unless P = NP and give an algorithm with approximation factor slightly larger than 2 for typical buffers. For the case of a single inverting buffer type, we give an algorithm with approximation factor slightly larger than 4.• We give local-improvement and clustering based MBRP heuristics with improved practical performance, and present a comprehensive experimental study comparing the runtime/quality tradeoffs of the proposed MBRP heuristics on test cases extracted from recent industrial designs.

Pre-bond testable low-power clock tree design for 3D stacked ICs

“…If the slew rate is too low, i.e., if it takes too long time for the clock signal to rise to 1 or fall to 0, the FF setup and hold time are affected, which will eventually slow down the clock. Existing work on slew-aware clock tree synthesis relies on buffer insertion [12,4,5,7]. Buffers are added along the clock paths so that the output load of each buffer is limited to a certain upper bound.…”

Multi-scenario buffer insertion in multi-core processor designs

“…For each buffer, there is a limit on the load capacitance it can drive [3]. Denote by max cap the maximum load capacitance any buffer can drive.…”

Multicommodity Flow Algorithms for Buffered Global Routing

“…Instead of spanning trees, we suggest to use buffered Steiner trees. The minimum buffered routing for the entire k-pin net can be found using one of the algorithms from [6]. Such routing has been shown to be very close to optimal and is convenient for handling high fanout nets -both sink and wire loads are taken into account.…”

“…Although the use of inverting buffers introduces additional polarity constraints, which may require a larger number of buffers to be inserted, overall inverting buffers may lead to a better overall resource utilization. Algorithms for bounded capacitive load inverting (and non-inverting) buffer insertion have been recently discussed in [6]. The focus of [6] is on single net buffering, with arbitrary positions for the buffers.…”

“…Algorithms for bounded capacitive load inverting (and non-inverting) buffer insertion have been recently discussed in [6]. The focus of [6] is on single net buffering, with arbitrary positions for the buffers. In our approach, the goal is to minimize the overall number of buffers required by the nets, and buffers can be inserted only in the available sites.…”