Hot-carrier current modeling and device degradation in surface-channel p-MOSFETs

Ong, T.C.; Ko, P.K.; Hu, Chenming

doi:10.1109/16.55753

Cited by 105 publications

(28 citation statements)

References 33 publications

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“…Maximum sensitivity to the induced degradation is observed when the damaged region is located at the source side of the pinched-off channel (i.e., reversed S/D current flow). After [46] interpretation of the degradation in the drain current characteristics, other characterization techniques, such as modified lateral-profiling charge pumping are often used [47]. In order to estimate the device time-to-failure (s) under Hot Carrier stress, several device parameter shifts have been alternatively used in literature as failure criteria, including fixed threshold voltage shift DV th , drain current reduction in the linear regime DI Dlin , transconductance degradation Dg m , or charge pumping current increase DI cp [48].…”

Section: Hot Carrier Degradationmentioning

confidence: 97%

Degradation Mechanisms

Franco

Kaczer

Groeseneken

2013

Reliability of High Mobility SiGe Channel MOSFETs for Future CMOS Applications

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In this chapter, a general description of the main MOSFET degradation mechanisms considered in this work is given. The proposed dissertation, while not aiming to give a complete coverage of the wide literature available on the treated topics, is meant to provide the reader with a sufficient basis to follow the discussion of the original experimental work presented in the following chapters.Most of the chapter is devoted to the Negative Bias Temperature Instability (NBTI) since this degradation mechanism pertains to most of the original experimental work on SiGe and Ge channel devices presented later in the Chaps. 4 Recent modeling attempts are focused on the central role of hole trapping mechanisms in NBTI degradation. However, the standard Shockley-Read-Hall models for carrier generation-recombination have been proven to be incapable of correctly capturing the properties of hole trapping into bulk oxide defects (Sect. 2.2.7). A physically more accurate description of the trapping mechanism, including vibrational motion of the atoms at the defect sites, is needed for reproducing the observed trapping behavior (Sect. 2.2.8). Based on these insights, a defect model compatible with a wide range of NBTI degradation observations J. Franco et al., Reliability of High Mobility SiGe Channel MOSFETs for Future

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Section: Hot Carrier Degradationmentioning

confidence: 97%

Degradation Mechanisms

Franco

Kaczer

Groeseneken

2013

Reliability of High Mobility SiGe Channel MOSFETs for Future CMOS Applications

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“…Also, the substrate current consists of hot holes originated from impact ionization so that there is an assumption that the degradation is proportional to the impact ionization [7,8]. However, in the recent studies, it has been observed that the lifetime of the devices does not follow the tendency of substrate current and it seems that there are two strong degradation bias conditions at (V G ~ V D /2) and (V G ~ V D ) [9][10][11].…”

Section: Introductionmentioning

confidence: 99%

3D TCAD Analysis of Hot-Carrier Degradation Mechanisms in 10 nm Node Input/Output Bulk FinFETs

Son¹,

Jeon²,

Kang³

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, we investigated the hotcarrier injection (HCI) mechanism, one of the most important reliability issues, in 10 nm node Input/Output (I/O) bulk FinFET. The FinFET has much intensive HCI damage in Fin-bottom region, while the HCI damage for planar device has relatively uniform behavior. The local damage behavior in the FinFET is due to the geometrical characteristics. Also, the HCI is significantly affected by doping profile, which could change the worst HCI bias condition. This work suggested comprehensive understanding of HCI mechanisms and the guideline of doping profile in 10 nm node I/O bulk FinFET.

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“…Contrary to the situation in n-MOSFETs, the amount of stress induced interface states in p-MOSFETs appears to be negligible [5]. Instead, stress-related breakdown gives rise to hot-electron injection into the gate oxide near drain, creating a permanent negative gate charge in this region, which results in a positive shift in the (negative) threshold voltage near drain and a significant increase in the drain current [6]. Although the threshold voltage shift in this case only takes place in a small part of the channel near drain, the increase in the saturation current is still as much as 15 %, without changing the overall threshold voltage for transition to subthreshold operation.…”

Section: Introductionmentioning

confidence: 68%

Enhanced p-MOSFET performance by channel field redistribution

Fjeldly

Ballangrud

Proceedings of the 1998 Second IEEE International Caracas Conference on Devices, Circuits and Systems. ICCDCS 98. On the 70th A

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We discuss how the performance of pchannel MOSFETs can be improved by introducing a variable threshold voltage along the conducting channel. The threshold voltage variation is designed to increase the charge carrier concentration near the drain, thereby increasing the saturation voltage and the saturation current, and improving the device speed. The effect was demonstrated experimentally by subjecting p-MOSFETs to high-bias stress, which creates a step-variation in the threshold voltage near drain. We also developed device models for pMOSFETs with linearly variable threshold, and predict that more than 40 % speed gain may be achieved in some cases.

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Hot-carrier current modeling and device degradation in surface-channel p-MOSFETs

Cited by 105 publications

References 33 publications

Degradation Mechanisms

Degradation Mechanisms

3D TCAD Analysis of Hot-Carrier Degradation Mechanisms in 10 nm Node Input/Output Bulk FinFETs

Enhanced p-MOSFET performance by channel field redistribution

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