Hot-carrier analysis on nMOS Si FinFETs with solid source doped junction

Chasm, Adrian; Franco, J.; Ritzenthaler, R.; Hellings, Geert; Cho, Moonju; Sasaki, Y.; Subirats, A.; Roussel, Philippe; Kaczer, B.; Linten, Dimitri; Horiguchi, N.; Groeseneken, G.; Thean, Aaron

doi:10.1109/irps.2016.7574535

Cited by 14 publications

(5 citation statements)

References 9 publications

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“…traps. This is because our previous studies conducted using the same FinFETs as in this work [28] showed no recovery of the degradation traces after removal of HC stress, while charge capture by border traps results in recoverable damage [8].…”

Section: The Modeling Frameworkmentioning

confidence: 62%

Bi-Modal Variability of nFinFET Characteristics During Hot-Carrier Stress: A Modeling Approach

Makarov

Kaczer

Chasin

et al. 2019

IEEE Electron Device Lett.

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We present a statistical analysis of the cumulative impact of random traps (RTs) and dopants (RDs) on hotcarrier degradation (HCD) in n-channel FinFETs. Calculations are performed at three combinations of high stress voltages and for conditions close to the operating regime. We generate 200 different configurations of devices with RDs and subsequently solve the Boltzmann transport equation to obtain the continuous interface trap concentration Nit. These deterministic densities Nit for each individual configuration are randomized and converted to 200 different configurations of RTs, yielding a total amount of 40,000 samples in our study. The analysis shows that at high stress voltages (with both RTs and RDs taken into account) probability densities of linear drain currents and device lifetimes are close to a bi-modal normal distribution, while in the operating regime such a trend is not visible.

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Section: The Modeling Frameworkmentioning

confidence: 62%

Bi-Modal Variability of nFinFET Characteristics During Hot-Carrier Stress: A Modeling Approach

Makarov

Kaczer

Chasin

et al. 2019

IEEE Electron Device Lett.

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“…This type of damage was suggested to contribute to HCD [16,37,38] as well as to so-called non-equilibrium bias temperature instability [39,40]. However, the samples employed in the current study did not feature significant recovery of ∆I d,lin and ∆I d,sat changes [32,41]. Thus, trapping of hot carriers by oxide traps is not considered here.…”

Section: Devices and Experimentsmentioning

confidence: 81%

“…nFinFETs have a gate length of L G = 40 nm, an operating voltage V dd of 0.9 V (the threshold voltage V th is ∼0.4 V), and a gate stack made of SiO 2 and HfO 2 layers with an equivalent oxide thickness of 1.2 nm [32]. The FinFETs were subjected to hot-carrier stress under three combinations of gate and drain voltages (V gs and V ds ): V gs = 1.7 V, V ds = 1.6 V; V gs = 1.8 V, V ds = 1.7 V; and V gs = 1.9 V, V ds = 1.8 V. These combinations of stress voltages correspond to the worst-case conditions of hot-carrier degradation for short-channel devices, i.e.…”

Section: Devices and Experimentsmentioning

confidence: 99%

Understanding and Modeling Opposite Impacts of Self-Heating on Hot-Carrier Degradation in n- and p-Channel Transistors

Tyaginov

Makarov²,

El-Sayed

et al. 2022

2022 IEEE International Reliability Physics Symposium (IRPS)

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We extend our framework for hot-carrier degradation (HCD) modeling by covering the impact of self-heating (SH) on HCD. This impact is threefold: (i) perturbation of carrier transport, (ii) acceleration of the thermal contribution to the Si-H bond breakage process, and (iii) and shortening vibrational lifetime of the bond resulting in reducing the multiple-carrier mechanism rate. We validate the framework against HCD data acquired on n-channel fin field-effect-transistors (FETs) and pchannel nanowire (NW) FETs under various stress conditions and analyze the importance of each of the aforementioned components of the SH impact on HCD. This analysis shows that in n-channel devices SH depopulates the high energetical fraction of the carrier distribution, while in p-channel transistors SH slightly shifts the carrier energy distribution towards higher energy. Thus, in nFinFETs the impact of SH on the carrier transport and enhancement of the thermal component of bond rupture compensate each other (vibrational lifetime shortening has a weak impact on HCD), thereby leading to slight inhibition of HCD by SH. To the contrary, in pNWFETs these two factors both enhance HCD (while the contribution of the vibrational lifetime dependence on temperature is again small) and thus SH accelerates HCD. Our modeling framework, therefore, can explain why in n-channel FETs SH slightly inhibits HCD, while in p-channel devices HCD is accelerated by SH.

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“…The results are shown in Fig. 6 The negative shift of the threshold voltage at strong electric fields in the gate oxide, caused by the gate electrode charge in the ion implantation process, is associated with the capture of holes released by lattice atoms ionization by a strong electric field [9,10]. Subsequent partial compensation of this shift is due to the electrons capture.…”

Section: Methodsmentioning

confidence: 98%

Electrostatic Charges and Ion Implantation Impact on the MIS Transistors Parameters Degradation

Mustafayev¹,

Cherkesova²,

Khasanov³

et al. 2019

Proceedings of the International Symposium "Engineering and Earth Sciences: Applied and Fundamental Research" Dedicated to the

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Resistance to electrostatic charges is one of the most important problems limiting the very large scale integrated circuits reliability. Increased currents cause the degradation of the instruments characteristics, similar to the degradation that occurs when hot electrons stream passes through. In order to increase the very large scale integrated circuits reliability, under hot electrons occurrence, exposure to ionizing radiation, electrostatic charges, and ion treatment, it is necessary to study the MIS transistors parameters degradation mechanisms. The results of the study show that the maximum the threshold voltage shift occurs when aluminum is sprayed onto the structure with a floating gate. The reason for the MIS transistors characteristics degradation is the charges of the gate electrode and the current in the oxide arising from strong electric fields. The degree of characteristics degradation in the hot electrons injection case does not depend on the energy of the ions bombarding the substrate surface.

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Hot-carrier analysis on nMOS Si FinFETs with solid source doped junction

Cited by 14 publications

References 9 publications

Bi-Modal Variability of nFinFET Characteristics During Hot-Carrier Stress: A Modeling Approach

Bi-Modal Variability of nFinFET Characteristics During Hot-Carrier Stress: A Modeling Approach

Understanding and Modeling Opposite Impacts of Self-Heating on Hot-Carrier Degradation in n- and p-Channel Transistors

Electrostatic Charges and Ion Implantation Impact on the MIS Transistors Parameters Degradation

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