Horizontally aligned ZnO nanowire transistors using patterned graphene thin films

Kim, Hwansoo; Park, Jihoon; Suh, Misook; Ahn, Joung Real; Ju, Sanghyun

doi:10.1063/1.3684614

Cited by 18 publications

(14 citation statements)

References 37 publications

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“…where q is the electronic charge, r nw is the NW radius, and l ($41 cm 2 /VÁs) is the reported mobility of the ZnO NWs grown from the MGF. 8 Here, the ZnO NW resistivity (q s ) is calculated to be $1.14 Â 10 À2 XÁcm. Incorporating a nonzero contact resistance would decrease (increase) the extracted q s (N D ) value.…”

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confidence: 99%

Nanoscale contacts between semiconducting nanowires and metallic graphenes

et al. 2012

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Here we report on the metal-semiconductor junction characteristics of a semiconducting ZnO nanowire grown directly on a metallic graphene film. The extracted specific contact resistivity of the graphene-ZnO nanowire contact (1.5 Â 10 À5 XÁcm 2) is comparable to that reported for Al-ZnO contacts. Based on the assumption that thermionic-field emission is the dominant mechanism, we obtained a zero-bias effective barrier height of 0.413 eV for the graphene-ZnO nanowire Schottky contact. We thus demonstrate that as a result of the enhanced tunneling at the contact, the graphene-nanowire contact exhibits near-ohmic current-voltage characteristics with a low contact resistance. V

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confidence: 99%

Nanoscale contacts between semiconducting nanowires and metallic graphenes

et al. 2012

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“…Typical bottom-up approaches involve nanowire synthesis by chemical vapour deposition (CVD) or a hydrothermal process, both of which result in high quality nanowires in terms of monocrystallinity, homogeneous morphology and a high aspect ratio, although the nanowire width and length can vary [10], [11]. However, bottom-up fabricated nanowires are difficult to be deposited at well defined positions on device substrates, which reduces the NWFET yield after subsequent top-down process steps that define other elements such as the source and drain electrodes at predetermined positions [12], [13], [14]. Recent investigations on bottom up technqiues show very controllable defenition of the nanowires to the substrate, but are also very cost intensive due to the use of electron beam lithography [15], [16].…”

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confidence: 99%

Multichannel ZnO nanowire field effect transistors by lift-off process

et al. 2018

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This paper describes a new, low-cost, top-down fabrication process, which makes it possible to define nanowire field effect transistor arrays with different numbers of nanowires simultaneously and systematically comparing their electrical performance. The main feature of this process is a developed bilayer photoresist pattern with a retrograde profile, which enables the modification of the nanowire in width, length, height and the number of transistor channels. The approach is compatible with low-cost manufacture without electron beam lithography, and benefits from process temperatures below 190 °C. Process reliability has been investigated by scanning electron microscopy, transmission electron microscopy and atomic force microscopy. Electrical measurements demonstrate enhancement mode transistors, which show a scalable correlation between the number of nanowires and the electrical characteristics. Devices with 100 nanowires exhibit the best performance with a high field effect mobility of 11.0 cm Vs, on/off current ratio of 3.97 × 10 and subthreshold swing of 0.66 V dec.

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“…The graphene layer, used as gate and source-drain electrodes, was grown on a Ni foil in a conventional thermal chemical vapor deposition system. 16) A separately grown graphene layer was transferred to the whole area of the device substrate and a photoresist (PR) was left only on the areas of source, drain, and gate electrodes. To complete the fabrication of the device, a single-step graphene transfer process, in which only source-gate-drain electrodes were kept after the non-PR coated graphene area was removed using the argon-based dry etching process (power of $150 W and time of $60 s), was employed, and gate and source-drain electrodes were formed simultaneously.…”

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Fabrication of Highly Transparent Nanowire Transistors with One-Step-Processed Graphene Gate–Source–Drain Electrodes

Bong

Han

Lee

et al. 2013

Appl. Phys. Express

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We report the fabrication of a highly transparent nanowire transistor using graphene as the gate and source-drain electrodes. Graphene gatesource-drain electrodes were simultaneously formed by a single-step transfer process. The graphene electrode and the nanowire channel exhibited near-ohmic contact characteristics. The threshold voltage, subthreshold slope, and mobility of the fabricated top-gate-structural In 2 O 3 nanowire transistor with graphene gate-source-drain electrodes were À4:54 V, 0.43 V/dec, and 78 cm 2 /(VÁs) respectively. The optical transmissions in the region that contained nanowire transistors on the quartz substrate were 88.5-90.3% in the 400-780 nm wavelength range.

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Horizontally aligned ZnO nanowire transistors using patterned graphene thin films

Cited by 18 publications

References 37 publications

Nanoscale contacts between semiconducting nanowires and metallic graphenes

Nanoscale contacts between semiconducting nanowires and metallic graphenes

Multichannel ZnO nanowire field effect transistors by lift-off process

Fabrication of Highly Transparent Nanowire Transistors with One-Step-Processed Graphene Gate–Source–Drain Electrodes

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