Horizontal DPA Attacks against ECC: Impact of Implemented Field Multiplication Formula

Microprocessors and Microsystems

Klann

et al. 2021

Self Cite

In this paper we discuss the difficulties of mounting successful attack against crypto implementations when essential information is missing. We start with a detailed description of our attack against our own design, to highlight which information is needed to increase the success of an attack, i.e. we use it as a blueprint to the following attack against commercially available crypto chips. We would like to stress that our attack against our own design is very similar to what happens during certification e.g. according to Common Criteria Standard as in those cases the manufacturer need to provide detailed information. When attacking the commercial designs without signing NDAs, we needed to intensively search the Internet for information about the designs. We cannot to reveal the private keys used by the attacked commercial authentication chips 100% correctly. Moreover, the missing knowledge of the used keys does not allow us to evaluate the success of our attack. We were able to reveal information on the processing sequence during the authentication process even as detailed as identifying the clock cycles in which the individual key bits are processed. To summarize the effort of such an attack is significantly higher than the one of attacking a well-known implementation.

Section: Industrial Authentications Productsmentioning

confidence: 93%

On the Complexity of Attacking Commercial Authentication Products

Microprocessors and Microsystems

Klann

et al. 2021

Self Cite

“…In our recent works [29][30][31], we investigated the influence of the activity of different field multipliers on the resistance of kP designs against horizontal SCA attacks. In [29], we investigated the application of the dummy activity of the multiplier as a means to reduce the vulnerability of our hardware accelerator for a single EC, P-256, to horizontal attacks.…”

Section: Influence Of Dummy Partial Multiplications On the Design Res...mentioning

confidence: 99%

Atomicity and Regularity Principles Do Not Ensure Full Resistance of ECC Designs against Single-Trace Attacks

Langendoerfer

2022

Sensors

Elliptic curve cryptography (ECC) is one of the commonly used standard methods for encrypting and signing messages which is especially applicable to resource-constrained devices such as sensor nodes that are networked in the Internet of Things. The same holds true for wearable sensors. In these fields of application, confidentiality and data integrity are of utmost importance as human lives depend on them. In this paper, we discuss the resistance of our fast dual-field ECDSA accelerator against side-channel analysis attacks. We present our implementation of a design supporting four different NIST elliptic curves to allow the reader to understand the discussion of the resistance aspects. For two different target platforms—ASIC and FPGA—we show that the application of atomic patterns, which is considered to ensure resistance against simple side-channel analysis attacks in the literature, is not sufficient to prevent either simple SCA or horizontal address-bit DPA attacks. We also evaluated an approach which is based on the activity of the field multiplier to increase the inherent resistance of the design against attacks performed.

“…The activity of the field multiplier can increase the inherent resistance of kP designs against SCA attacks. To exploit the field multiplier as a countermeasure different multiplication methods have to be combined [22]. We didn't find any information about the implementation of such a countermeasure in industrial chips.…”

Section: Background: Verical and Horizontal Attacksmentioning

confidence: 99%

Horizontal Attacks Against ECC: From Simulations to ASIC

Lecture Notes in Computer Science

Klann

et al. 2020

Self Cite

In this paper we analyse the impact of different compile options on the success rate of side channel analysis attacks. We run horizontal differential side channel attacks against simulated power traces for the same kP design synthesized using two different compile options after synthesis and after layout. As we are interested in the effect on the produced ASIC we also run the same attack against measured power traces after manufacturing the ASIC. We found that the compile_ultra option reduces the success rate significantly from 5 key candidates with a correctness of between 75 and 90 per cent down to 3 key candidates with a maximum success rate of 72 per cent compared to the simple compile option. Also the success rate after layout shows a very high correlation with the one obtained attacking the measured power and electromagnetic traces, i.e. the simulations are a good indicator of the resistance of the ASIC.