Horizontal Attacks Against ECC: From Simulations to ASIC

Microprocessors and Microsystems

Klann

et al. 2021

Self Cite

In this paper we discuss the difficulties of mounting successful attack against crypto implementations when essential information is missing. We start with a detailed description of our attack against our own design, to highlight which information is needed to increase the success of an attack, i.e. we use it as a blueprint to the following attack against commercially available crypto chips. We would like to stress that our attack against our own design is very similar to what happens during certification e.g. according to Common Criteria Standard as in those cases the manufacturer need to provide detailed information. When attacking the commercial designs without signing NDAs, we needed to intensively search the Internet for information about the designs. We cannot to reveal the private keys used by the attacked commercial authentication chips 100% correctly. Moreover, the missing knowledge of the used keys does not allow us to evaluate the success of our attack. We were able to reveal information on the processing sequence during the authentication process even as detailed as identifying the clock cycles in which the individual key bits are processed. To summarize the effort of such an attack is significantly higher than the one of attacking a well-known implementation.

Section: B Implementation Details Of Our Kp Designmentioning

confidence: 99%

On the Complexity of Attacking Commercial Authentication Products

Microprocessors and Microsystems

Klann

et al. 2021

Self Cite

“…In [5], [10] the comparison to the mean attack was introduced. It is based on the fact that the measured kP trace is a sequence of the processing of '1' and '0' values of the scalar k. We call the samples in the trace representing the processing of a single bit of the scalar a slot.…”

Section: Comparison To the Mean Attackmentioning

confidence: 99%

“…Parameters of the designs synthesized for the 250 nm cell library are given in section III. Sections IV describes a horizontal DPA attack using the comparison to the mean [10] for revealing the key. Section V shortly describes an automated simple power analysis (SPA) attack.…”

Section: Introductionmentioning

confidence: 99%

Breaking a fully Balanced ASIC Coprocessor Implementing Complete Addition Formulas on Weierstrass Elliptic Curves

2020 23rd Euromicro Conference on Digital System Design (DSD)

Klann

et al. 2020

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In this paper we report on the results of selected horizontal SCA attacks against two open-source designs that implement hardware accelerators for elliptic curve cryptography. Both designs use the complete addition formula to make the point addition and point doubling operations indistinguishable. One of the designs uses in addition means to randomize the operation sequence as a countermeasure. We used the comparison to the mean and an automated SPA to attack both designs. Despite all these countermeasures, we were able to extract the keys processed with a correctness of 100%.

“…The latter allows then impersonation, falsifying digital signatures etc. During our earlier work we learnt that the compiler options used during synthesis have a significant impact on the SCA vulnerability of the resulting implementation even for ASICs [1]. This triggered the idea that similar might hold true for FPGA implementations as well.…”

Section: Introductionmentioning

confidence: 99%

On the Influence of the FPGA Compiler Optimization Options on the Success of the Horizontal Attack

Sosa

2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

et al. 2019

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This paper reports about the impact of compiler options on the resistance of cryptographic implementations against side channel analysis attacks. We evaluated four compiler option for six different FPGAs from Intel and Xilinx. In order to ensure fair assessment we synthesized always the same VHDL code, kept the measurement setup and statistical analysis method etc. constant. Our analysis clearly shows that the compiler options have an impact on the success of attacks but also that the impact is unpredictable not only between different FPGAs but also for an individual FPGA.