Holistic approach for overlay and edge placement error to meet the 5nm technology node requirements

Mulkens, Jan; Slachter, Bram; Kubis, Michael; Tel, Wim; Hinnen, Paul; Maslow, Mark John; Dillen, Harm; Ma, Eric; Chou, Kevin; Liu, Xuedong; Ren, Weiming; Hu, Xuerang; Wang, Fei; Liu, Kevin

doi:10.1117/12.2297283

Cited by 24 publications

(22 citation statements)

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“…This new lithography method will reduce the manufacturing complexity since it enables the return to the use of single exposure method to pattern the critical layers. 241 There are many challenges for the fabrication of transistors at this scale and complexity, which have to be dealt and solved. Radamson et al reviewed the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and how the process flow faces different technological challenges.…”

Section: Ltemmentioning

confidence: 99%

Review of THz-based semiconductor assurance

True

Jessurun

et al. 2021

Opt. Eng.

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Terahertz radiation for inspection and fault detection has been of interest for the semiconductor industry since the first generation and detection of THz signals. Until recent hardware advances, THz systems lacked the signal quality and reliability for use as an effective nondestructive testing (NDT) method. Incremental advances in THz sources, detectors, and signal processing resulted in the successful applied-industrial use of THz NDT techniques on carbon fiber laminates, automotive coatings, and for detection of counterfeit pharmaceutical tablets. Semiconductor inspection and verification methods ensure the functionality and thereby safety of vital electronics for several critical industries. For this reason, the reliability and verification of a THz NDT method must exceed currently used inspection systems. With recent laboratory access to THz radiation, THz inspection methods are often compared with existing optical, electrical, and volumetric semiconductor verification techniques for their production monitoring and failure analysis viability. This review will cover THz techniques and their applications at the printed circuit board (PCB), integrated circuit (IC), and transistor/gate scales. The THz radiation gap spans between optical and electronic ranges with a millimeter-sized wavelength allowing for adequate penetration of plastic and ceramic and semiconductor materials. THz radiation can be used to determine structural features, electrical signatures in the THz range, and chemical information simultaneously. Cost and environmental limitations restricted the ability for THz NDT semiconductor inspection methods to escape the lab and succeed in the dynamic environment of a semiconductor fabrication environment. Hybridized metrology methods incorporating information from multiple inspection tools are a regime where THz spectral and structural data can be combined with existing methods such as optical, x-ray, or E-beam. THz can be used initially to offer support to the complex failure analysis and verification requirements of the semiconductor industry from nanoscale to macroscale features and components. For THz systems to become independent inspection tools used for semiconductor production monitoring, in the lab or fab, this will require a confident level of statistical process control for THz signal generation, detection, or processing. Applied industrial semiconductor device inspection will likely be a result of a combination of research into THz hardware, reconstruction techniques, and the widespread application of machine learning techniques. Many breakthroughs occurred over the years to enable successful nondestructive characterization and inspection of semiconductor devices from the nanoscale transistors to fully packaged integrated circuits and assembled PCBs.

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Section: Ltemmentioning

confidence: 99%

Review of THz-based semiconductor assurance

True

Jessurun

et al. 2021

Opt. Eng.

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“…When asymmetry is present 1,8 , a careful selection of recipe is necessary to minimize the error in overlay and such selection procedures were discussed in previous publications 2,3 . For the majority of the production stacks at current production nodes, these procedures are adequate (e.g., selection of a single wavelength / polarization condition that operates near the peak of the signal swing curve).…”

Section: Grating Imbalance Grating Asymmetrymentioning

confidence: 99%

“…In multi patterning processes, overlay is now entangled with CD including OPC and stochastics 1 . This combined effect is called Edge Placement Error (EPE) and it is the key metrics for patterning budget generation and holistic patterning control.…”

Section: Introductionmentioning

confidence: 99%

Tough road ahead for device overlay and edge placement error

Bhattacharyya

2019

Metrology, Inspection, and Process Control for Microlithography XXXIII

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During the last several years we have seen an impressive drive in the industry to continue to innovate in order to keep up with the challenging requirements of overlay in multi-patterning processes. A major part of these efforts is spent in opening up of the flexibility in control knobs on process tools (mostly lithography and etch) enabling the high order actuation capability. In order to feed this high order actuation, it has also become important to address the need of input data accuracy, driving up the demand for improved metrology accuracy and sampling. Adding to the complexity, it has also become important to address edge placement error (EPE). EPE is basically the pattern fidelity of a device structure created by a multi-patterning process, defined as the relative displacement of the edges of two features from their intended target position. Here local CD error is an important parameter in addition to overlay. EPE requirements of a "single digit nanometer number" is now a harsh reality in 5nm nodes and below. In this technical presentation we will review the above developments and remaining gaps in technology (litho and dimensional metrology applications), as well as design and integration. Mitigation of such challenges need a large team effort that is industry-wide and not just limited to litho.

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“…This technology also defines the upcoming challenges for equipment and processes along the production line among which wafer-level overlay and CD error requirements stand out most prominent. Mulkens et al described how they contribute to a common metric, the edge placement error (EPE) [1]. Within the EPE budget the contribution due to resist and photon stochastics becomes larger with advanced nodes and is the hardest or is even impossible to come by.…”

Section: Introductionmentioning

confidence: 99%

New registration calibration strategies for MBMW tools by PROVE measurements

Haberler

Hudek²,

Jurkovic³

et al. 2022

37th European Mask and Lithography Conference

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EUV lithography is currently setting the pace for the semiconductor industry’s expectations on future progress towards the 3nm node and beyond. This technology also defines the upcoming challenges for equipment providers upstream and downstream of the production line among which wafer-level overlay and CD error requirements stand out most prominent. Registration errors on the mask, both local (mid-range) and global (long-range), contribute to overlay errors on the wafer. Here, we will present novel calibration strategies for the IMS Multi-Beam Mask Writer (MBMW) by ZEISS PROVE measurements to meet the mask registration requirements: First, we showcase how we can efficiently leverage the high precision, resolution and fast capture time of the PROVE tool to allow for extensive control and tuning of MBMW properties that affect local registration (LREG) such as systematic residual errors originating from the electron beam optics. Second, we provide insights into the MBMW Registration Improvement Correction (RIC) calibrated with PROVE technology. This feature allows removing remaining systematic local registration errors in the MBMW electron beam array field (82μm x 82μm) resulting in LREG improvement by 30% from 1.2nm to 0.8nm three-sigma. Third, we show how the PROVE technology can be applied efficiently for the calibration of the MBMW’s Thermal Expansion Correction (TEC) that allows compensating systematic global registration errors originating from thermal-mechanical deformations of the mask during the writing process.

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Holistic approach for overlay and edge placement error to meet the 5nm technology node requirements

Cited by 24 publications

References 0 publications

Review of THz-based semiconductor assurance

Review of THz-based semiconductor assurance

Tough road ahead for device overlay and edge placement error

New registration calibration strategies for MBMW tools by PROVE measurements

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