Hole-Injection-Type and Electron-Injection-Type Silicon Avalanche Photodiodes Fabricated by Standard 0.18-$\mu$m CMOS Process

Iiyama, Koichi; Takamatsu, Hideki; Minamikawa, Takeo

doi:10.1109/lpt.2010.2047389

Cited by 47 publications

(23 citation statements)

References 8 publications

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“…2(a) is same with the nMOS structure in a P-substrate and then is referred to as the nMOS-type CMOS-APD. This structure was referred as the electron-injection-type CMOS-APD in our previous paper [13]. Due to the shorted GR, the photo-generated electrons in the P-substrate and DNW move toward n + -layers on the DNW because of the built-in potential barrier between the Pwell and the DNW, while photo-generated holes in the P-substrate move toward the p + -layers on the Psubstrate because of the built-in potential barrier between the P-substrate and the DNW, and photo-generated holes in the DNW move toward the p + -layer on the Pwell.…”

Section: Copyright Cmentioning

confidence: 99%

“…2(b) is same with the pMOS structure in a P-substrate and is referred to as the pMOStype CMOS-APD. This structure was referred as the holeinjection-type CMOS-APD in our previous paper [13]. The photo-generated electrons in the P-substrate move to the n + -layers on the Nwell, and the photo-generated holes move to the p + -layers on the P-substrate due to the built-in potential barrier between the P-substrate and the Nwell, and they are recombined and do not contribute to the photocurrent.…”

Section: Copyright Cmentioning

confidence: 99%

“…One solution is to add guard ring (GR) structure in the CMOS-APD [1,11]. We have studied CMOS-APDs with interdigital electrode structure for high-speed data transmission systems [12][13] and for Blu-ray optical disc system [14]. The CMOS-APDs with bandwidth over 1 GHz and the avalanche gain of more than 100 have been realized.…”

Section: Introductionmentioning

confidence: 99%

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Characterizing Silicon Avalanche Photodiode Fabricated by Standard 0.18µm CMOS Process for High-Speed Operation

Napiah

Gyobu

Hishiki

et al. 2016

IEICE Trans. Electron.

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SUMMARYnMOS-type and pMOS-type silicon avalanche photodiodes (APDs) were fabricated by standard 0.18 µm CMOS process, and the current-voltage characteristic and the frequency response of the APDs with and without guard ring structure were measured. The role of the guard ring is cancellation of photo-generated carriers in a deep layer and a substrate. The bandwidth of the APD is enhanced with the guard ring structure at a sacrifice of the responsivity. Based on comparison of nMOS-type and pMOS-type APDs, the nMOS-type APD is more suitable for high-speed operation. The bandwidth is enhanced with decreasing the spacing of interdigital electrodes due to decreased carrier transit time and with decreasing the detection area and the PAD size for RF probing due to decreased device capacitance. The maximum bandwidth was achieved with the avalanche gain of about 10. Finally, we fabricated a nMOS-type APD with the electrode spacing of 0.84 µm, the detection area of 10 × 10 µm 2 , the PAD size for RF probing of 30 × 30 µm 2 , and with the guard ring structure. The maximum bandwidth of 8.4 GHz was achieved along with the gain-bandwidth product of 280 GHz.

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Section: Copyright Cmentioning

confidence: 99%

Section: Copyright Cmentioning

confidence: 99%

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Characterizing Silicon Avalanche Photodiode Fabricated by Standard 0.18µm CMOS Process for High-Speed Operation

Napiah

Gyobu

Hishiki

et al. 2016

IEICE Trans. Electron.

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“…Si PDs fabricated by complementary metal oxide semiconductor (CMOS) process are promising optical devices for easy integration with electronic circuits without any process modification, and avalanche photodiode fabricated by CMOS process (CMOS-APD) has been developed for optical interconnection applications [1]- [3]. We have studied CMOS-APDs with interdigital electrode structure for high-speed data transmission systems [4], [5] and for Bluray optical disc systems [6]. The CMOS-APDs with bandwidth over 1 GHz and the avalanche gain of more than 100 have been proposed and realized.…”

Section: Introductionmentioning

confidence: 99%

Optimizing silicon avalanche photodiode fabricated by standard CMOS process for 8 GHz operation

Zul

Iiyama

Gyobu

et al. 2015

2015 1st International Conference on Telematics and Future Generation Networks (TAFGEN)

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Abstract-Silicon avalanche photodiode (APD) was fabricated by standard 0.18 μm CMOS process. The current-voltage characteristic and frequency response was measured for the APD with and without guard ring. With the existent of guard ring around the perimeter of the diode junction, it shows a better performance for the maximum bandwidth but in contrast it shows lower in responsivity. For the first time, an optimizing of electrode spacing, detection area and the PAD size for RF probing shows an enhancement of the bandwidth. The detection area and the PAD size for RF probing are reduced to 10 x 10 μm² and 30 x 30 μm², respectively, to decrease the device capacitance, the spacing of interdigital electrode is narrowed to 0.84 μm to decrease carrier transit time, and by cancelling the carriers photo-generated in the deep layer and the substrate because the carriers are slow diffusion carriers. As a result, the maximum bandwidth of 8.0 GHz was achieved along with gain-bandwidth product of 280 GHz.

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“…CMOS-PDs realized with standard CMOS technology are typically very slow due to slow diffusion photocurrents produced in the substrate as 850-nm light has much longer penetration depth than the narrow depletion regions possible in standard CMOS technology. Several approaches have been tried to overcome this limitation [17][18][19], [22][23][24][25][26][27]. Recently, a 10-Gb/s CMOS-Rx was reported with a high-speed spatially-modulated PD (SM-PD) [18].…”

Section: Introductionmentioning

confidence: 99%

A fully-integrated 125-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector

Lee¹,

Youn²,

Park³

et al. 2014

Opt. Express

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We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxidesemiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOScompatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

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Hole-Injection-Type and Electron-Injection-Type Silicon Avalanche Photodiodes Fabricated by Standard 0.18-$\mu$m CMOS Process

Cited by 47 publications

References 8 publications

Characterizing Silicon Avalanche Photodiode Fabricated by Standard 0.18µm CMOS Process for High-Speed Operation

Characterizing Silicon Avalanche Photodiode Fabricated by Standard 0.18µm CMOS Process for High-Speed Operation

Optimizing silicon avalanche photodiode fabricated by standard CMOS process for 8 GHz operation

A fully-integrated 125-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector

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