Holding voltage investigation of advanced SCR-based protection structures for CMOS technology

Tazzoli, Augusto; Marino, Fabio Alessio; Cordoni, Martina; Benvenuti, A.; Colombo, Paolo; Zanoni, Enrico; Meneghesso, G.

doi:10.1016/j.microrel.2007.07.078

Cited by 13 publications

(5 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…According to the previous work [17], the holding voltage (V h ) of the SCR device under dc measurement was much lower than that of the same SCR device under TLP measurement. However, a different measured result has been observed in the NMOS-triggered SCR devices in this paper.…”

Section: B Discussionmentioning

confidence: 75%

Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection

Chen

Ker

2009

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

MOS-triggered silicon-controlled rectifier (SCR) devices have been reported to achieve efficient on-chip electrostatic discharge (ESD) protection in deep-submicrometer CMOS technology. The channel length of the embedded MOS transistor in the MOS-triggered SCR device dominates the trigger mechanism and current distribution to govern the trigger voltage, holding voltage, on resistance, second breakdown current, and ESD robustness of the MOS-triggered SCR device. The embedded MOS transistor in the MOS-triggered SCR device should be optimized to achieve the most efficient ESD protection in advanced CMOS technology. In addition, the layout style of the embedded MOS transistor can be adjusted to improve the MOS-triggered SCR device for ESD protection.

show abstract

Section: B Discussionmentioning

confidence: 75%

Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection

Chen

Ker

2009

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

show abstract

“…7. The holding voltages of the ESD protection circuits under dc measurement are lower than those under TLP measurement due to the self-heating effect [22]. The test circuits B, D, E, F, and G exhibit dc larger than (2.5 V) with at least 10% margin, which are very safe from latchup event.…”

Section: Latchup Immunitymentioning

confidence: 93%

Large-Swing-Tolerant ESD Protection Circuit for Gigahertz Power Amplifier in a 65-nm CMOS Process

Lin

Tsai

Chu

et al. 2013

IEEE Trans. Microwave Theory Techn.

View full text Add to dashboard Cite

The signal swing at output pad of some radio-frequency (RF) power amplifiers (PAs) may be higher than the supply voltage. To protect the gigahertz large-swing power amplifier from electrostatic discharge (ESD) damage in nanoscale CMOS process, a large-swing-tolerant ESD protection circuit is presented in this paper. The proposed ESD protection circuit had been designed, fabricated, and characterized in a 65-nm CMOS process, where it can achieve low parasitic capacitance, large swing tolerance, high ESD robustness, and good latchup immunity. The proposed ESD protection circuit had been further applied to a 2.4-GHz PA to provide 3-kV human-body-model (HBM) ESD robustness without degrading the RF performances. Index Terms-Electrostatic discharge (ESD), power amplifier (PA), radio-frequency (RF), silicon-controlled rectifier (SCR).

show abstract

“…可控硅 (silicon controlled rectifier, SCR) 作为一种ESD防护结构, 其有较好的面积效率, 常被用作高效ESD防护结构. Wang等 [13] 研究了SCR在高温下的触发与维持特性. Tazzoli等 [14] 提出了一种高维持电压的SCR, 研究了 SCR的温度依赖特性, 发现ESD脉冲时间导致的自加热效应会导致维持电压变化.…”

Section: 一般来说 Esd防护结构设计应遵循esd设计窗unclassified

Effect of high-temperature on holding characteristics in MOSFET ESD protecting device

Li¹,

Cai²,

Zeng³

et al. 2022

Acta Phys. Sin.

View full text Add to dashboard Cite

The holding voltage of electrostatic discharge (ESD) protective structure is the critical parameter to determine the latch-up performance of the protecting device, but the thermal change of ESD device parameters exposes the protecting device to latch-up risk in high ambient temperature. In this paper, the holding characteristics of the ESD protection device under various ambient temperatures ranging from 30 to 195℃℃ are studied. The investigated ESD structure is the NMOS transistors fabricated with the 0.18 μm partially depleted silicon-on-insulator (PDSOI) process. The ESD characteristics of the device are measured by the transmission line pulse (TLP) test system at different ambient temperatures. The test results show that the holding voltage (VH) decreases with the increasing temperature. TCAD simulation is carried out to support and analyze the experiment results, and the same trend of VH versus temperature is obtained. Through the analysis of simulation results and theoretical derivation, the underlying physical mechanisms related to the effects of temperature on VH and holding current (IH) are discussed in detail. When the Drain is subject to the same current pulsing, Source and Body is grounded, the distributions of current density, electric potential, and injected electron density of NMOS under various temperatures are extracted and analyzed. When the Drain, Source, and Body are grounded, the distributions of the electrostatic field under various temperatures are extracted and analyzed. The distributions of electric potential in NMOS indicate that voltage drop on the Drain-Body junction (VDB) is affected by ambient temperature significantly, and the variation of VDB dominates the variation trend of VH with increasing temperature. The decreasing electrostatic field and increasing injected electron density with decreasing temperature contribute to the decreasing VDB. The trend of IH and parasitic Body resistance (RBody) weakens the temperature dependence of the VH. The current gain of parasitic bipolar transistor (β) decreases with growing ambient temperature, which is the main contributor to the decreasing IH. Therefore, increasing IH and RBody is helpful to reduce the temperature dependence of the latch-immune ESD protection structure.

show abstract

Holding voltage investigation of advanced SCR-based protection structures for CMOS technology

Cited by 13 publications

References 5 publications

Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection

Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection

Large-Swing-Tolerant ESD Protection Circuit for Gigahertz Power Amplifier in a 65-nm CMOS Process

Effect of high-temperature on holding characteristics in MOSFET ESD protecting device

Contact Info

Product

Resources

About