HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping

Lavin, Christopher; Padilla, Marc; Lamprecht, Jaren; Lundrigan, Philip; Nelson, Brent; Hutchings, Brad

doi:10.1109/fccm.2011.17

Cited by 83 publications

(33 citation statements)

References 18 publications

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“…Our analysis relied heavily upon the open source tool RapidSmith [19] developed at Brigham Young University. RapidSmith is a Java API that is able to both parse Xilinx design files and interface with part databases.…”

Section: Analysis Of Resultsmentioning

confidence: 99%

A Fault Injection Analysis of Linux Operating on an FPGA-Embedded Platform

Monson

Wirthlin

Hutchings

2012

International Journal of Reconfigurable Computing

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An FPGA-based Linux test-bed was constructed for the purpose of measuring its sensitivity to single-event upsets. The test-bed consists of two ML410 Xilinx development boards connected using a 124-pin custom connector board. The Design Under Test (DUT) consists of the "hard core" PowerPC, running the Linux OS and several peripherals implemented in "soft" (programmable) logic. Faults were injected via the Internal Configuration Access Port (ICAP). The experiments performed here demonstrate that the Linux-based system was sensitive to 199,584 or about 1.4 percent of all tested bits. Each sensitive bit in the bit-stream is mapped to the resource and user-module to which it configures. A density metric for comparing the reliability of modules within the system is presented. Using this density metric, we found that the most sensitive user module in the design was the PowerPC's direct connections to the DDR2 memory controller.

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Section: Analysis Of Resultsmentioning

confidence: 99%

A Fault Injection Analysis of Linux Operating on an FPGA-Embedded Platform

Monson

Wirthlin

Hutchings

2012

International Journal of Reconfigurable Computing

Self Cite

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Section: Motivationmentioning

confidence: 99%

“…While some of the related research [12] relocates post-place netlists, others [13][14] [15] relocate post-route netlists, which are also known as hard macros in a Xilinx context. For example, in HMFlow [13], a simulated annealing macro placer is developed and swaps hard macros using module relocation to achieve better placement results. Although [25] obtained significant speedups in the place-and-route process, the compilation flow cannot guarantee the speedups when logic utilization is above 50% and the resulted clock rates can only achieve 75% of the clock rates resulted from Xilinx tools.…”

Section: Motivationmentioning

confidence: 99%

Rapid Overlay Builder for Xilinx FPGAs

Yue

Koch

Lemieux

2015

2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines

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A field-programmable gate array (FPGA) is a type of programmable hardware, where a logic designer must create a specific hardware design and then "compile" it into a bitstream that "configures" the device for a specific function at power-up. This compiling process, known as place-and-route (PAR), can take hours or even days, a duration which discourages the use of FPGAs for solving compute-oriented problems. To help mitigate this and other problems, overlays are emerging as useful design patterns in solving compute-oriented problems. An overlay consists of a set of compiler-like tools and an architecture written in a hardware design language like VHDL or Verilog. This cleanly separates the compiling problem into two phases: at the front end, high-level language compilers can quickly map a compute task into the overlay architecture, which is now serving as an intermediate layer. Unfortunately, the back-end of the process, where an overlay architecture is compiled into an FPGA device, remains a very time-consuming task. Many attempts have been made to accelerate the PAR process, ranging from using multicore processors, making quality/runtime tradeoffs, and using hard macros, with limited success. We introduce a new hard-macro methodology, called Rapid Overlay Builder, and demonstrate a run-time improvement up to 22 times compared to a regular unaccelerated flow using Xilinx ISE. In addition, compared to prior work, ROB continues to work well even with high logic utilization levels of 89%, and it consistently maintains high clock rates. By applying this methodology, we anticipate that overlays can be implemented much more quickly and with lower area and speed overheads than would otherwise be possible. This will greatly improve the usability of FPGAs, allowing them to be used as a replacement for CPUs in a greater variety of applications.

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“…The repair tool is constructed on RapidSmith [34,35], which is a set of Java-based application programming interface (API) s, offering access to the low-level resources of the FPGA. This way, RapidSmith provides an easy way of building up specific purpose computer-aided design tools for Xilinx FPGAs.…”

Section: Fig 9 Routing Repaired Bcdl Simplified Aes In Which T/f S-bmentioning

confidence: 99%

Sophisticated security verification on routing repaired balanced cell‐based dual‐rail logic against side channel analysis

Bhasin

Otero

et al. 2015

IET Information Security

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Conventional dual-rail precharge logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the counterpart rails. As a light-weight and high-speed dual-rail style, balanced cell-based dual-rail logic (BCDL) uses synchronised compound gates with global precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security-sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)-co-processor is executed that is constructed on block random access memory (RAM)-based BCDL in Xilinx Virtex-5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non-identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL.

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HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping

Cited by 83 publications

References 18 publications

A Fault Injection Analysis of Linux Operating on an FPGA-Embedded Platform

A Fault Injection Analysis of Linux Operating on an FPGA-Embedded Platform

Rapid Overlay Builder for Xilinx FPGAs

Sophisticated security verification on routing repaired balanced cell‐based dual‐rail logic against side channel analysis

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