HiveFlex-Video VSP1: Video Signal Processing Architecture for Video Coding and Post-Processing

Pinto, C.A. Alba; Beric, A.; Singh, Satendra Pal; Farfade, Sachin

doi:10.1109/ism.2006.83

Cited by 10 publications

(7 citation statements)

References 3 publications

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“…Instruction and data level parallelism exploited in BMC implementation, scalability, small processor's memory footprint and reduced number of transfers with external memory, made possible real-time implementation on Intel's mobile platform. The concepts, features and possibilities of the Video Signal Processor architecture are explained in [28] . The tackled challenges in obtaining real-time performance with minimal processing power are explained more in [29] .…”

Section: Resultsmentioning

confidence: 99%

Block-Matching Correlation Motion Estimation for Frame-Rate up-Conversion

KovaăźEvić

Pantić

Beric

et al. 2015

J Sign Process Syst

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This paper proposes a novel motion estimation algorithm that combines recursive block-matching and customized phase plane correlation. In comparison with alternative approaches the proposed solution shows better subjective impressions and objective measurements, such as Peak Signal to Noise Ratio and Universal Image Quality Index. Computational complexity of the algorithm is constrained and suitable for real-time implementations on platforms with limited memory and processing resources. The proof of concept is the first real-time implementation of frame-rate up-conversion on a mobile platform (Intel Merrifield), which is capable of processing 1080p video at 30 frames per second while clocked at 200 MHz.

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Section: Resultsmentioning

confidence: 99%

Block-Matching Correlation Motion Estimation for Frame-Rate up-Conversion

KovaăźEvić

Pantić

Beric

et al. 2015

J Sign Process Syst

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show abstract

“…TCTPE-2DX [21] added some special instructions into TCTPE to support the pixel level image processing and the 2D image processing. The area of TCTPE-2DX increases to 0.222 mm 2 . In order to support high resolution image processing, general purpose communication module is removed and message-passing fashion the communication pipeline which is optimized for parallel image processing is equipped into the system.…”

Section: Performance and Area Evaluationmentioning

confidence: 92%

“…Several data is computed in parallel; therefore, a wider data memory (64 bit) [2], [18] is commonly adopted in SIMD architecture processors. However, the performance of processing which uses look-up table cannot be effectively improved by using SIMD architecture [18] due to the single I/O of the data memory.…”

Section: Design Of Multi Bank Architecture For Pixel Level Imagementioning

confidence: 99%

“…However, this is a time-consuming and costly solution. In order to ease the time-to-market pressures and to maximize design reusability, programmable or reconfigurable hardware has been gradually proposed [1], [2]. The variety of processing is one of the issues in the implementation of image processing engines, and performance requirements turn out to be another issue.…”

Section: Introductionmentioning

confidence: 99%

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Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing

Liao

Asri

Isshiki

et al. 2013

Journal of Information Processing

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An image processing engine is an important component in generating high quality images in video systems. Processing during capture and display are non-standard and vary from case by case, hence, the flexibility of image processing engines has turned out to be an important issue. The conventional hardware type of image processing engine such as an Application Specific Integrated Circuit (ASIC) is not applicable for this case. In order to increase design reusability and ease time-to-market pressures, Application Specific Instruction-set Processors (ASIP) which provide high flexibility and high computational efficiency have emerged as a promising solution. In this paper, we present two ASIPs. PXL ASIP, which has a reconfigurable multi bank memory module and an SIMD type computation pipeline, is designed for pixel level image processing, while 2D ASIP, which has slide register module and reconfigurable ALU modules, is designed for 2D image processing. PXL ASIP can perform 4 to 10 times faster compared to its base processor, and 2D ASIP can perform 5 to 43 times faster compared to its base processor.

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“…To meet those a certain number of Operations-Per-Second (OPS) needs to be executed. In the case of AVC Baseline Profile encoding at HDTV 720p resolution at 30 frames-per-second, this minimum performance is in the order of 100 integer GigaOPS (GOPS), depending on specific encoder algorithmic implementations and settings [10,20,31]. The only way to deliver this and consume acceptable amounts of energy is through parallelization.…”

Section: Multimedia Application Opportunitiesmentioning

confidence: 99%

Design and Tool Flow of Multimedia MPSoC Platforms

Sutter

Verkest

Brockmeyer

et al. 2008

J Sign Process Syst Sign Image Video Technol

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This paper surveys components that are useful to build programmable, predictable, composable, and scalable multiprocessor-system-on-a-chip (MPSoC) multimedia platforms that can deliver high performance at high power-efficiency. A design-time tool flow is proposed to exploit all forms of parallelism on such platforms. As a first proof of concept, the flow is used to parallelize a relatively simple video standard on a platform consisting of off-the-shelf components. As a second proof of concept, we present the design of a high-performance platform with state-of-theart components. This platform targets real-time H.264 high-definition video encoding at an estimated power consumption of 700 mW.

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HiveFlex-Video VSP1: Video Signal Processing Architecture for Video Coding and Post-Processing

Cited by 10 publications

References 3 publications

Block-Matching Correlation Motion Estimation for Frame-Rate up-Conversion

Block-Matching Correlation Motion Estimation for Frame-Rate up-Conversion

Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing

Design and Tool Flow of Multimedia MPSoC Platforms

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