2020
DOI: 10.1116/1.5131656
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Highly uniform silicon field emitter arrays fabricated using a trilevel resist process

Abstract: Load line analysis showing AIE used to calculate the current sensitivity for field emitter tips with radius r 1 < r 2 < r 3 (blue lines) in series with (a) small or large resistor, (b) FET or nanowire, and (c) FET or nanowire with reduced tip radius distribution (red lines).

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Cited by 19 publications
(9 citation statements)
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References 27 publications
(34 reference statements)
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“…The III-N SAGFEAs demonstrated in this work are also compared with SAGFEAs based on other materials (Fig. 5(b)) [3], [4], [8], [26]- [28]. When setting an overdrive voltage (V OV = V GE -V GE,ON ) of 20 V, the J A of our AlGaN SAGFEAs approaches 100 mA/cm 2 and is comparable with state-of-the-art Si SAGFEAs.…”
Section: Resultsmentioning
confidence: 51%
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“…The III-N SAGFEAs demonstrated in this work are also compared with SAGFEAs based on other materials (Fig. 5(b)) [3], [4], [8], [26]- [28]. When setting an overdrive voltage (V OV = V GE -V GE,ON ) of 20 V, the J A of our AlGaN SAGFEAs approaches 100 mA/cm 2 and is comparable with state-of-the-art Si SAGFEAs.…”
Section: Resultsmentioning
confidence: 51%
“…5. (a) S-K chart of fabricated III-N self-align-gated FEAs and (b) benchmark of different materials FEAs[3],[4],[8],[26]-[28]. The same-color labels in (a) represent F-N parameters of different transfer characteristics from one FEA after conditioning.…”
mentioning
confidence: 99%
“…Such CNTs are typically bundled [55][56][57] and slightly bent, conditions that are incompatible with use as nanocantilevers. A silicon-based massive nanocantilever 58 and field emitter 59,60 have been fabricated using a semiconductor process.…”
Section: Introductionmentioning
confidence: 99%
“…Additionally, pattern transfer into an anti-reflective coating utilizing a nitrogen plasma largely simplifies the ability to achieve a highly homogeneous polymer soft mask [51]. Moreover, DTLbased mask patterns are suitable for use in CM-ICP RIE systems to achieve SiNW arrays at the wafer scale, which can then be allocated to a specific location on the substrate in areas of μm 2 -cm 2 sizes by applying a hybrid lithography step [52,53].…”
Section: Introductionmentioning
confidence: 99%